Patents by Inventor Hung-Ping Tsai
Hung-Ping Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130141Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Applicant: United Microelectronics Corp.Inventors: Ya-Huei Tsai, Rai-Min Huang, Yu-Ping Wang, Hung-Yueh Chen
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Patent number: 8963296Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.Type: GrantFiled: January 31, 2014Date of Patent: February 24, 2015Assignee: Vishay General Semiconductor, LLCInventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
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Publication number: 20140217561Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.Type: ApplicationFiled: January 31, 2014Publication date: August 7, 2014Applicant: VISHAY GENERAL SEMICONDUCTOR, LLCInventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
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Patent number: 8643152Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.Type: GrantFiled: February 27, 2012Date of Patent: February 4, 2014Assignee: Vishay General Semiconductor, LLCInventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
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Publication number: 20120223421Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.Type: ApplicationFiled: February 27, 2012Publication date: September 6, 2012Applicant: VISHAY GENERAL SEMICONDUCTOR, LLCInventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
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Patent number: 8125056Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.Type: GrantFiled: September 23, 2009Date of Patent: February 28, 2012Assignee: Vishay General Semiconductor, LLCInventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
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Publication number: 20110068439Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.Type: ApplicationFiled: September 23, 2009Publication date: March 24, 2011Applicant: VISHAY GENERAL SEMICONDUCTOR, LLC.Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
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Patent number: 6291316Abstract: A wafer-level process for fabricating a plurality of passivated semiconductor devices comprising the steps of providing a semiconductor wafer on that at least one p-n junction is formed, Cutting a plurality of grooves in said wafer to expose said at least one p-n junction, wherein each of said grooves extends partly through the wafer and has a depth that is enough to expose said at least one p-n junction, applying a passivating material into said grooves and curing the material. The grooves can be formed by using a disc saw having a blade, by performing a sandblasting operation within a controlled operation time, or by performing a photolithographically chemical etching process. The passivating material is either screen-printed or pin-dispensed into the grooves. A dicing operation can be subsequently proceeded to divide the wafer into individual chips for subsequent fabrication into completed semiconductor devices.Type: GrantFiled: January 19, 1999Date of Patent: September 18, 2001Assignee: General Semiconductor of Taiwan, LTDInventors: Christopher Michael Knowles, Yih-Yin Lin, Tung-Chieh Lin, William John Nelson, Hung-Ping Tsai, Richard Sean O'Rourke