Patents by Inventor Hung-Sheng Chang
Hung-Sheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996866Abstract: A feedback control system configured to drive a load is disclosed. The feedback control system includes an up-sampling circuit, configured to perform an un-sampling operation on a source signal and produce an up-sampled signal with an up-sampling frequency according to the up-sampled signal and a feedback signal from the load; a delta circuit, coupled to the up-sampling circuit and configured to produce a delta signal; a sigma circuit, configured to produce a density modulation signal according to the delta signal; and a driving device, configured to drive the load according to the density modulation signal with the up-sampling frequency.Type: GrantFiled: March 6, 2023Date of Patent: May 28, 2024Assignee: xMEMS Labs, Inc.Inventors: Jemm Yue Liang, Hsi-Sheng Chen, Chieh-Yao Chang, Hung-Chi Huang, Jing-Meng Liu
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Publication number: 20240139935Abstract: A three-dimensional measuring device includes a ball-shaped structure, an X-axis measuring module, a Y-axis measuring module and a Z-axis measuring module. The ball-shaped structure is moved and/or rotated in response to a movement of a movable object. The X-axis measuring module includes a first measuring structure and a first position sensor. The first measuring structure is movable along an X-axis direction and contacted with the ball-shaped structure. The Y-axis measuring module includes a second measuring structure and a second position sensor. The second measuring structure is movable along a Y-axis direction and contacted with the ball-shaped structure. The Z-axis measuring module includes a third measuring structure and a third position sensor. The third measuring structure is movable along a Z-axis direction and contacted with the ball-shaped structure.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Inventors: Chi-Huan Shao, Chih-Ming Hsu, Chi-Shun Chang, Hung-Sheng Chang
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Publication number: 20240147606Abstract: An electronic device includes a first substrate structure, multiple electronic elements and a second substrate structure. The first substrate structure includes a first substrate. The electronic elements are disposed on the first substrate. The second substrate structure is coupled to the first substrate structure. The second substrate structure includes a second substrate, a protection circuit, a driving circuit and a bonding pad. The protection circuit is disposed on the second substrate. The driving circuit is disposed on the second substrate and configured to drive at least a part of the electronic elements. The bonding pad is disposed on the second substrate. The protection circuit is respectively coupled to the bonding pad and the driving circuit. The electronic device may reduce the damage caused by electrostatic discharge or reduce the impact of the bonding process of the bonding pad on signal conduction.Type: ApplicationFiled: September 14, 2023Publication date: May 2, 2024Applicant: Innolux CorporationInventors: Mu-Fan Chang, Yi-Hua Hsu, Hung-Sheng Liao, Min-Hsin Lo, Ming-Chun Tseng, Ker-Yih Kao
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Publication number: 20240127754Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.Type: ApplicationFiled: December 7, 2023Publication date: April 18, 2024Inventors: Chin-Wei Lin, Hung Sheng Lin, Shih Chang Chang, Shinya Ono
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Patent number: 11934480Abstract: A circuit for in-memory multiply-and-accumulate functions includes a plurality of NAND blocks. A NAND block includes an array of NAND strings, including B columns and S rows, and L levels of memory cells. W word lines are coupled to (B*S) memory cells in respective levels in the L levels. A source line is coupled to the (B*S) NAND strings in the block. String select line drivers supply voltages to connect NAND strings on multiple string select lines to corresponding bit lines simultaneously. Word line drivers are coupled to apply word line voltages to a word line or word lines in a selected level. A plurality of bit line drivers apply input data to the B bit lines simultaneously. A current sensing circuit is coupled to the source line.Type: GrantFiled: July 10, 2019Date of Patent: March 19, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hang-Ting Lue, Hung-Sheng Chang, Yi-Ching Liu
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Publication number: 20240088267Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yi PENG, Chih Chieh YEH, Chih-Sheng CHANG, Hung-Li CHIANG, Hung-Ming CHEN, Yee-Chia YEO
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Patent number: 11904464Abstract: A three-dimensional measuring device includes a ball-shaped structure, an X-axis measuring module, a Y-axis measuring module and a Z-axis measuring module. The ball-shaped structure is moved and/or rotated in response to a movement of a movable object. The X-axis measuring module includes a first measuring structure and a first position sensor. The first measuring structure is movable along an X-axis direction and contacted with the ball-shaped structure. The Y-axis measuring module includes a second measuring structure and a second position sensor. The second measuring structure is movable along a Y-axis direction and contacted with the ball-shaped structure. The Z-axis measuring module includes a third measuring structure and a third position sensor. The third measuring structure is movable along a Z-axis direction and contacted with the ball-shaped structure.Type: GrantFiled: September 17, 2020Date of Patent: February 20, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Chi-Huan Shao, Chih-Ming Hsu, Chi-Shun Chang, Hung-Sheng Chang
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Patent number: 11550709Abstract: A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.Type: GrantFiled: October 17, 2019Date of Patent: January 10, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wei-Chen Wang, Hung-Sheng Chang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo
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Patent number: 11526285Abstract: A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.Type: GrantFiled: September 9, 2019Date of Patent: December 13, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wei-Chen Wang, Hung-Sheng Chang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo
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Patent number: 11526328Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.Type: GrantFiled: February 4, 2020Date of Patent: December 13, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hung-Sheng Chang, Han-Wen Hu, Hsiang-Pang Li, Tzu-Hsien Yang, I-Ching Tseng, Hsiang-Yun Cheng, Chia-Lin Yang
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Patent number: 11504863Abstract: A heat dissipation device and a robot using the same are provided. The heat dissipation device comprises a porous material layer, a transporting tube and a liquid. The at least one porous material layer is disposed on a housing surface of a robot. The porous material layer has an evaporation surface and an accommodation space. The evaporation surface is disposed through and exposed from the housing surface. The evaporation surface and the accommodation space are in fluid communication with each other. The transporting tube is connected to the at least one porous material layer and in fluid communication with the accommodation space. The liquid is transported into the at least one accommodation space through the transporting tube and exposed from the evaporation surface. Thus, the liquid evaporates at the evaporation surface to reduce a temperature of the housing surface of the robot via convection and evaporation.Type: GrantFiled: June 19, 2020Date of Patent: November 22, 2022Assignee: DELTA ELECTRONICS, INC.Inventors: Chi-Huan Shao, Hung-Sheng Chang
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Patent number: 11354123Abstract: A computing in memory method for a memory device is provided. The computing in memory method includes: based on a stride parameter, unfolding a kernel into a plurality of sub-kernels and a plurality of complement sub-kernels; based on the sub-kernels and the complement sub-kernels, writing a plurality of weights into a plurality of target memory cells of a memory array of the memory device; inputting an input data into a selected word line of the memory array; performing a stride operation in the memory array; temporarily storing a plurality of partial sums; and summing the stored partial sums into a stride operation result when all operation cycles are completed.Type: GrantFiled: September 21, 2020Date of Patent: June 7, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hung-Sheng Chang, Han-Wen Hu, Yueh-Han Wu, Tse-Yuan Wang, Yuan-Hao Chang, Tei-Wei Kuo
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Patent number: 11119674Abstract: A memory device includes an array of composite memory units. At least one of the composite memory units comprises a first memory cell of a first type, a second memory cell of a second type, a first intra-unit data path connecting the first memory cell to the second memory cell, and a first data path control switch. The first data path control switch is responsive to a data transfer enable signal which enables data transfer between the first memory cell and the second memory cell through the first intra-unit data path.Type: GrantFiled: February 19, 2019Date of Patent: September 14, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hung-Sheng Chang, Han-Wen Hu
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Publication number: 20210240443Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.Type: ApplicationFiled: February 4, 2020Publication date: August 5, 2021Applicant: MACRONIX International Co., Ltd.Inventors: Hung-Sheng Chang, Han-Wen Hu, Hsiang-Pang Li, Tzu-Hsien Yang, I-Ching Tseng, Hsiang-Yun Cheng, Chia-Lin Yang
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Publication number: 20210162584Abstract: A three-dimensional measuring device includes a ball-shaped structure, an X-axis measuring module, a Y-axis measuring module and a Z-axis measuring module. The ball-shaped structure is moved and/or rotated in response to a movement of a movable object. The X-axis measuring module includes a first measuring structure and a first position sensor. The first measuring structure is movable along an X-axis direction and contacted with the ball-shaped structure. The Y-axis measuring module includes a second measuring structure and a second position sensor. The second measuring structure is movable along a Y-axis direction and contacted with the ball-shaped structure. The Z-axis measuring module includes a third measuring structure and a third position sensor. The third measuring structure is movable along a Z-axis direction and contacted with the ball-shaped structure.Type: ApplicationFiled: September 17, 2020Publication date: June 3, 2021Inventors: Chi-Huan Shao, Chih-Ming Hsu, Chi-Shun Chang, Hung-Sheng Chang
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Publication number: 20210138669Abstract: A heat dissipation device and a robot using the same are provided. The heat dissipation device comprises a porous material layer, a transporting tube and a liquid. The at least one porous material layer is disposed on a housing surface of a robot. The porous material layer has an evaporation surface and an accommodation space. The evaporation surface is disposed through and exposed from the housing surface. The evaporation surface and the accommodation space are in fluid communication with each other. The transporting tube is connected to the at least one porous material layer and in fluid communication with the accommodation space. The liquid is transported into the at least one accommodation space through the transporting tube and exposed from the evaporation surface. Thus, the liquid evaporates at the evaporation surface to reduce a temperature of the housing surface of the robot via convection and evaporation.Type: ApplicationFiled: June 19, 2020Publication date: May 13, 2021Inventors: Chi-Huan Shao, Hung-Sheng Chang
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Publication number: 20210117187Abstract: A computing in memory method for a memory device is provided. The computing in memory method includes: based on a stride parameter, unfolding a kernel into a plurality of sub-kernels and a plurality of complement sub-kernels; based on the sub-kernels and the complement sub-kernels, writing a plurality of weights into a plurality of target memory cells of a memory array of the memory device; inputting an input data into a selected word line of the memory array; performing a stride operation in the memory array; temporarily storing a plurality of partial sums; and summing the stored partial sums into a stride operation result when all operation cycles are completed.Type: ApplicationFiled: September 21, 2020Publication date: April 22, 2021Inventors: Hung-Sheng CHANG, Han-Wen HU, Yueh-Han WU, Tse-Yuan WANG, Yuan-Hao CHANG, Tei-Wei KUO
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Patent number: 10967527Abstract: A brake release device and a robot manipulator employing the same are provided. The robot manipulator includes a housing and a brake element. The housing defines an inner space and has an opening, and the inner space is in communication with a space outside the housing through the opening. The brake element is disposed within the inner space. The robot manipulator stops or is allowed to actuate according to a position of the brake element. The brake release device is connected with the brake element. The brake release device is partially located in the inner space, and the brake release device partially penetrates through the opening and is exposed from the housing. When the part of the brake release device exposed from the housing is moved by an external force so as to drive the brake element to move synchronously, the robot manipulator is allowed to actuate.Type: GrantFiled: March 4, 2019Date of Patent: April 6, 2021Assignee: DELTA ELECTRONICS, INC.Inventors: Chi-Huan Shao, Chih-Ming Hsu, Hung-Sheng Chang
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Patent number: 10891077Abstract: A flash memory device and a controlling method are provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module and a latency-aware module. The in-place update module is used for performing a program procedure or a garbage collection procedure via a bit erase operation or a page erase operation on the memory array. The out-of-place update module is used for performing the program procedure or the garbage collection procedure via a block erase operation or a migration operation on the memory array. The latency-aware module is used for determining a relationship between a first overhead of the in-place update module and a second overhead of the out-of-place update module.Type: GrantFiled: December 26, 2018Date of Patent: January 12, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hung-Sheng Chang, Hang-Ting Lue, Yuan-Hao Chang
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Patent number: 10859630Abstract: A circuit test method for a test device to test a device under test is provided. The circuit test method includes the steps of applying zero volts to a plurality of power pins of the device under test; applying a test voltage to a first signal pin among a plurality of signal pins of the device under test; and measuring a current on a second signal pin among the plurality of signal pins of the device under test and determining whether there is a leakage current in the device under test.Type: GrantFiled: November 15, 2017Date of Patent: December 8, 2020Assignee: SILICON MOTION, INC.Inventors: Hung-Sen Kuo, Te-Wei Chen, Hung-Sheng Chang, Ming-Wan Kuan