Abstract: A metal-insulation-metal (MIM) device including a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer is provided. The first insulation layer is disposed on the first metal layer. The second metal layer is disposed on a part of the first insulation layer. The second insulation layer is disposed on a side wall of the second metal layer and on another part of the first insulation layer. A width of the first insulation layer under the second metal layer and the second insulation layer parallel to the first metal layer is greater than a with of the second metal layer parallel to the first metal layer.

Abstract: A metal-insulation-metal (MIM) device including a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer is provided. The first insulation layer is disposed on the first metal layer. The second metal layer is disposed on a part of the first insulation layer. The second insulation layer is disposed on a side wall of the second metal layer and on another part of the first insulation layer. A width of the first insulation layer under the second metal layer and the second insulation layer parallel to the first metal layer is greater than a with of the second metal layer parallel to the first metal layer.

Abstract: A metal-insulation-metal (MIM) device including a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer is provided. The first insulation layer is disposed on the first metal layer. The second metal layer is disposed on a part of the first insulation layer. The second insulation layer is disposed on a side wall of the second metal layer and on another part of the first insulation layer. A width of the first insulation layer under the second metal layer and the second insulation layer parallel to the first metal layer is greater than a with of the second metal layer parallel to the first metal layer. A manufacture method of an MIM device is also provided.

Abstract: A metal-insulation-metal (MIM) device including a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer is provided. The first insulation layer is disposed on the first metal layer. The second metal layer is disposed on a part of the first insulation layer. The second insulation layer is disposed on a side wall of the second metal layer and on another part of the first insulation layer. A width of the first insulation layer under the second metal layer and the second insulation layer parallel to the first metal layer is greater than a with of the second metal layer parallel to the first metal layer. A manufacture method of an MIM device is also provided.

Abstract: An electrical-overstress (EOS) protection circuit for an electronic device includes series-connected resistors, a mode-control switch, and a bias circuit. The series-connected resistors are electrically coupled between an input and an output, and the mode-control switch is electrically coupled between the output and a ground. The bias circuit is electrically coupled to the input for generating a mode-control signal to control the mode-control switch. The bias circuit generates the mode-control signal in a way such that the mode-control switch is open in a normal mode and closed in an EOS mode.

Abstract: An electrical-overstress (EOS) protection circuit for an electronic device includes series-connected resistors, a mode-control switch, and a bias circuit. The series-connected resistors are electrically coupled between an input and an output, and the mode-control switch is electrically coupled between the output and a ground. The bias circuit is electrically coupled to the input for generating a mode-control signal to control the mode-control switch. The bias circuit generates the mode-control signal in a way such that the mode-control switch is open in a normal mode and closed in an EOS mode.

Abstract: An electrical-overstress (EOS) protection circuit for an electronic device includes series-connected resistors, a mode-control switch, and a bias circuit. The series-connected resistors are electrically coupled between an input and an output, and the mode-control switch is electrically coupled between the output and a ground. The bias circuit is electrically coupled to the input for generating a mode-control signal to control the mode-control switch. The bias circuit generates the mode-control signal in a way such that the mode-control switch is open in a normal mode and closed in an EOS mode.

Abstract: A method for fabricating a non-volatile memory having a P-type floating gate is described. A tunneling layer is formed on a substrate and then a first patterned polysilicon layer is formed on the tunneling layer. A buried drain is formed in the substrate beside the first polysilicon layer and then an insulating structure is formed on the tunneling layer on the buried drain. Thereafter, a second polysilicon layer is formed on the first polysilicon layer to constitute a floating gate together with the first polysilicon layer. A P-type ion is implanted into the second polysilicon layer and then a dielectric layer and a control gate are sequentially formed on the floating gate. A thermal process is then performed to make the P-type, ion in the second polysilicon layer diffuse into the first polysilicon layer.

Abstract: A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions to minimize the short-channel effects, a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide.

Abstract: A protection circuit scheme for electrostatic discharge, the protection circuit scheme includes the electrostatic discharge clamp circuit and the isolated circuit. The electrostatic discharge clamp circuit herein receives the electrostatic voltage from the signal input, and the isolated circuit receives the high frequency signal from the signal input. At the same time, the isolated circuit also isolates the direct bias from the internal circuit to prevent the loss of the latch up of the electrostatic discharge clamp circuit.

Abstract: An erasing method for a p-channel nitride read only memory. The method is used for a p-channel nitride read only memory having charges stored in a charge-trapping layer. A positive voltage is applied to the control gate and a negative voltage to the drain; also, the source is floating and the n-well is grounded. The voltage difference between the positive voltage applied to the control gate and the negative voltage to the drain is sufficient to trigger a band-to-band induced hot electron injection to erase the p-channel nitride read only memory.

Abstract: A method for operating a P-channel SONOS memory device that has a charge trapping layer located on a substrate, a gate electrode located on the trapping layer, two doped regions located in the substrate at each side of the charge trapping layer. The two doped regions are set to be a drain region and a source region. When a programming action is intended, the gate electrode and the drain region are applied with a first negative high-level bias, and the source region and the substrate are applied with a grounded voltage. When an erasing action is intended, the gate electrode is a second negative bias which is smaller than the first negative voltage in absolute value. In the mean time, the drain region is applied with the third negative bias and the substrate is applied with a grounded voltage. The third negative voltage is larger than the second negative bias in absolute value.

Abstract: An erasing method for a p-channel nitride read only memory. The method is used for a p-channel nitride read only memory having charges stored in a charge-trapping layer. A positive voltage is applied to the control gate and a negative voltage to the drain; also, the source is floating and the n-well is grounded. The voltage difference between the positive voltage applied to the control gate and the negative voltage to the drain is sufficient to trigger a band-to-band induced hot electron injection to erase the p-channel nitride read only memory.

Abstract: A method for fabricating a non-volatile memory having a P-type floating gate is described. A tunneling layer is formed on a substrate and then a first patterned polysilicon layer is formed on the tunneling layer. A buried drain is formed in the substrate beside the first polysilicon layer and then an insulating structure is formed on the tunneling layer on the buried drain. Thereafter, a second polysilicon layer is formed on the first polysilicon layer to constitute a floating gate together with the first polysilicon layer. A P-type ion is implanted into the second polysilicon layer and then a dielectric layer and a control gate are sequentially formed on the floating gate. A thermal process is then performed to make the P-type, ion in the second polysilicon layer diffuse into the first polysilicon layer.

Abstract: A semiconductor device with trench isolation structure is disclosed. The invention uses a trench isolation structure that can be formed by using conventional methods to prevent problems such as drain induced barrier lowering (DIBL), punch-through leakage and spiking leakage. Thus these poor electrical properties of the conventional semiconductor device with a shallow junction depth resulting from the shrink of design rules can be solved.

Abstract: A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions to minimize the short-channel effects, a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide.

Abstract: A method for fabricating a non-volatile memory is described. A planar doped region is formed in the substrate at first. A mask layer and a patterned photoresist layer are sequentially formed on the substrate. A plurality of trenches is formed in the substrate with the patterned photoresist layer as a mask to divide the planar doped region into a plurality of bit-lines. The patterned photoresist layer is removed and then a recovering process is performed to recover the side-walls and the bottoms of the trenches from the damages caused by the trench etching step; The mask layer is removed. A dielectric layer is formed on the substrate and then a plurality of word-lines is formed on the dielectric layer.

Abstract: A method for fabricating a non-volatile memory is described. A planar doped region is formed in the substrate at first. A mask layer and a patterned photoresist layer are sequentially formed on the substrate. A plurality of trenches is formed in the substrate with the patterned photoresist layer as a mask to divide the planar doped region into a plurality of bit-lines. The patterned photoresist layer is removed and then a recovering process is performed to recover the side-walls and the bottoms of the trenches from the damages caused by the trench etching step. The mask layer is removed. A dielectric layer is formed on the substrate and then a plurality of word-lines is formed on the dielectric layer.

Abstract: The present invention provides a memory structure, comprising: a substrate; a gate structure disposed on the substrate; a buried bit-line disposed in the substrate along both sides of the gate structures; a raised bit-line disposed on the buried bit-line; an isolating spacer disposed on both sidewalls of the gate structure and a word-line disposed over the substrate, wherein the word-line is electrically connected to the gate structure and isolated from the raised bit-line by an insulation layer.

Abstract: A method for fabricating a non-volatile memory is described. A planar doped region is formed in the substrate at first. A mask layer and a patterned photoresist layer are sequentially formed on the substrate. A plurality of trenches is formed in the substrate with the patterned photoresist layer as a mask to divide the planar doped region into a plurality of bit-lines. The patterned photoresist layer is removed and then a recovering process is performed to recover the side-walls and the bottoms of the trenches from the damages caused by the trench etching step. The mask layer is removed. A dielectric layer is formed on the substrate and then a plurality of word-lines is formed on the dielectric layer.