Abstract: Provided is a PCR device including a conveying module and a heat supply module. The conveying module includes: a bench; a rail being loop-style, allowing the bench to move along the rail; and at least one holder arranged on the bench, allowing at least one reactor tube to be detachably disposed at the at least one holder. The heat supply module includes at least one heat supply block for adjusting the temperature of the at least one reactor tube.

Abstract: A system, an apparatus, and a method for cloud resource allocation are provided. The cloud resource allocation system includes a plurality of worker nodes and a master node. The master node includes: an orchestrator configured to: obtain multiple node resource information respectively reported by a plurality the worker nodes through a resource manager; and parse a job profile of a job request obtained from the waiting queue through the job scheduler and decide to execute a direct resource allocation or a preemptive indirect resource allocation for a job to be handled requested by the job request based on the node resource information and the job profile.

Abstract: A semiconductor structure includes a semiconductor fin extending from a substrate, a source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the S/D feature, where the silicide layer extends along a sidewall of the S/D feature, and an etch-stop layer (ESL) disposed along a sidewall of the silicide layer.

Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A count of the first metal vias of the first net is less than a count of the second metal vias of the second net, and a line height of the first metal line of the first net is greater than a line height of the second metal line of the second net.

Abstract: There is provided an optical engine for a navigation device including a first light source, a second light source, a lens, a carrier member and an image sensor. The carrier member has a light holder, a lens holder, an accommodation space and a tilted wall. The first light source is arranged on the light holder of the carrier member, and reflected light associated with the first light source penetrates through the lens to propagate to the image sensor inside the accommodation space. Reflected light associated with the second light source penetrates through the tilted wall of the carrier member to propagate to the image sensor.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. The semiconductor device structure includes a silicide layer between the dielectric fin and the epitaxial structure. A void is between the silicide layer and the dielectric fin.

Abstract: A method includes forming a dielectric layer on a semiconductor workpiece, forming a first patterned layer of a first dipole material on the dielectric layer, and performing a first thermal drive-in operation at a first temperature to form a diffusion feature in a first portion of the dielectric layer beneath the first patterned layer. The method also includes forming a second patterned layer of a second dipole material, where a first section of the second patterned layer is on the diffusion feature and a second section of the second patterned layer is offset from the diffusion feature. The method further includes performing a second thermal drive-in operation at a second temperature, where the second temperature is less than the first temperature. The method additionally includes forming a gate electrode layer on the dielectric layer.

Abstract: An apparatus for novel high-speed low power non-volatile memory for the next generation electronic memory and computing technology is provided. The apparatus may include a ferroelectric tunnel junction (FTJ) that can switch between two or more conductance states in a reversible and non-volatile manner. A ferroelectric tunnel junction (FTJ) having two electrodes separated by a thin ferroelectric (FE) insulating layer has potential to replace existing volatile and non-volatile memory. Through the application of electrical pulses, the electrical resistance of an FTJ can be reversibly changed in a non-volatile manner by switching the ferroelectric polarization in the ferroelectric insulator layer.

Abstract: A resistive memory device includes a dielectric layer, a first via connection structure, a first stacked structure, and a first insulating structure. The first via connection structure is disposed in the dielectric layer. The first stacked structure is disposed on the first via connection structure and the dielectric layer. The first insulating structure penetrates through a portion of the first stacked structure in a vertical direction and divides the first stacked structure into a first cell unit and a second cell unit. The first cell unit and the second cell unit include a first shared bottom electrode, and the first insulating structure is disposed directly on the first shared bottom electrode.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.

Abstract: Methods, apparatus and systems for wireless sensing are described. In one example, a described system in a wireless data communication network comprises: a transmitter configured to transmit a time series of at least one wireless sounding signal (WSS) based on a standard wireless network protocol associated with the wireless data communication network, and a receiver. The wireless data communication network comprises a physical (PHY) layer, a medium access control (MAC) layer, and at least one higher layer. The receiver is configured to: receive the time series of at least one WSS (TSWSS) based on the standard wireless network protocol through a wireless channel of a venue, and perform a plurality of wireless sensing measurements based on the received TSWSS to obtain sensing measurement results based on the standard wireless network protocol.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: An antenna element comprises one or more directors, a resonator, and a three dimensional ground assembly. Parts of the antenna element are arranged on three metal layers. A top layer has an unconnected metal bar which forms a beam director, a resonator and a top part of the ground assembly. The resonator is an integral piece substantially in the form of a loop connected to a feed line and a feed line terminal ending. The feed line terminal ending serves as the ground plane for the feed line as well as providing impedance matching from the external transceiver circuit to the resonator. The ground assembly includes a top layer ground connected to a plurality of metallized half cylindrical hole channels (or metallized via holes) which connect to a ground terminal in a bottom layer.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.

Abstract: A keyboard and a key structure capable of displaying instant image thereof are provided. The key structure includes a display unit, a circuit membrane, an elastic member, a key seat, a first supporting frame, a second supporting frame, and a translucent keycap. The first supporting frame has two first arms and two axle portions. The ends of the first arms are slidably disposed on an accommodation portion of the key seat. The second supporting frame has two second arms and two linking holes. The ends of the second arms are pivotally connected to the accommodation portion. The linking hole is elongated-shaped. When the translucent keycap is not pressed, the axle portion abuts against one hole-end of the linking hole. When the translucent keycap is pressed, the axle portion abuts against another one hole-end of the linking hole.

Abstract: Methods, apparatus and systems for wireless sensing are described. In one example, a described system in a wireless data communication network comprises: a transmitter configured to transmit a time series of at least one wireless sounding signal (WSS) based on a standard wireless network protocol associated with the wireless data communication network, and a receiver. The wireless data communication network comprises a physical (PHY) layer, a medium access control (MAC) layer, and at least one higher layer. The receiver is configured to: receive the time series of at least one WSS (TSWSS) based on the standard wireless network protocol through a wireless channel of a venue, and perform a plurality of wireless sensing measurements based on the received TSWSS to obtain sensing measurement results based on the standard wireless network protocol.

Abstract: An electronic system test method, comprising: (a) inputting a victim test pattern to a victim signal path of a target electronic system and simultaneously inputting at least one aggressor test pattern to at least one aggressor signal path of the target electronic system, according to a major set of test patterns comprising a plurality of minor set of test patterns; (b) acquiring a output response corresponding to the step (a); and (c) after changing the victim test pattern or the aggressor test pattern, and after repeating the step (a) and the step (b) until all of the major test patterns set are used thereby acquiring a plurality of the output responses, determining a combination level according to the output responses. The victim test pattern is an X bit pattern and the aggressor test pattern is a Y bit pattern, X and Y are positive integers larger than or equal to 3.

Abstract: The present invention relates to a foamable composition used to prepare foamed thermoplastic polyurethane and a microwave molded body thereof. The foamable composition includes unfoamed thermoplastic polyurethane particles, a thickener or a bridging agent, and a foaming agent, wherein the unfoamed thermoplastic polyurethane particles have a viscosity of 1,000 poise to 9,000 poise measured at 170° C. according to JISK 7311 test method.

Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.