Patents by Inventor Hung-Wei Huang

Hung-Wei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240355393
    Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Inventors: Shih Kuang Yang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair, Chia-Sheng Lin
  • Publication number: 20240355729
    Abstract: Some implementations described herein include techniques and apparatus for forming a semiconductor device including a semiconductor resistor structure. The semiconductor resistor structure (e.g., a low-impedance thin-film resistor structure) may include a resistive layer having an approximately rectangular shape (e.g., a width-to-length ratio that is less than approximately one). The semiconductor resistor structure includes contact structures connected to the resistive layer, a conductive bus structure having an approximately rectangular shape that connects to the contact structures, and an electrical terminal (e.g., a routing pin) centrally located at or near an edge of the conductive bus structure.
    Type: Application
    Filed: April 21, 2023
    Publication date: October 24, 2024
    Inventors: Chun-Heng CHEN, Liang-Yi CHANG, Yu-Wei LIANG, Chang-Yu HUANG, Hung-Han LIN, Ru-Shang HSIAO
  • Publication number: 20240355741
    Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG
  • Publication number: 20240357948
    Abstract: Device structures and methods for forming the same are provided. A semiconductor structure according to the present disclosure includes a first electrode and a second electrode disposed over a substrate, a heating element disposed over the substrate, a phase-change material layer disposed over the substrate, and an insulator disposed vertically between the heating element and the phase-change material layer. The phase-change material layer includes at least a first segment and a second segment separated from the first segment. Each of the first and second segments overlaps the heating element in a top view. Each of the first and second segments is electrically connected with both the first and second electrodes.
    Type: Application
    Filed: April 18, 2023
    Publication date: October 24, 2024
    Inventors: Hung-Ju LI, Yu-Wei TING, Tsung-Hao YEH, Kuo-Pin CHANG, Kuo-Ching HUANG
  • Publication number: 20240345622
    Abstract: A portable electronic device including a first body, a second body, and a light module is provided. The second body is pivotally connected to the first body. The light module is adjacent to the second body and is disposed on the first body. The light module includes a frame, a light guide plate, a light source, a patterned light guide film, and a light-transmitting cover plate. The frame is disposed on the first body. The light guide plate is disposed in the frame and has a light incident surface and a light emitting surface. The light source is disposed in the frame as corresponding to the light incident surface of the light guide plate. The patterned light guide film is detachably disposed on the light guide plate and covers the light emitting surface. The light-transmitting cover plate is detachably disposed on the frame and covers the patterned light guide film.
    Type: Application
    Filed: November 20, 2023
    Publication date: October 17, 2024
    Applicant: Acer Incorporated
    Inventors: Hung-Chi Chen, Hsueh-Wei Chung, Pao-Ching Huang, Huei-Ting Chuang, Chao-Di Shen
  • Publication number: 20240338804
    Abstract: A method for high dynamic range imaging is provided. The method includes the following stages. A first image from a first sensor capable of sensing a first spectrum is received. A second image from a second sensor capable of sensing a second spectrum is received. The second spectrum has a higher wavelength range as compared to the first spectrum. A first image feature from the first image and a second image feature from the second image are retrieved. The first and second images are fused by referencing the first image feature and the second image feature to generate a final image.
    Type: Application
    Filed: April 6, 2023
    Publication date: October 10, 2024
    Inventors: Pin-Wei CHEN, Keh-Tsong LI, Shao-Yang WANG, Chia-Hui KUO, Hung-Chih KO, Yun-I CHOU, Yu-Hua HUANG, Yen-Yang CHOU, Chien-Ho YU, Chi-Cheng JU, Ying-Jui CHEN
  • Publication number: 20240341204
    Abstract: A semiconductor device includes a first film, a second film, and a third film that each include a phase change material (PCM) and are arranged with respect to one another along a first lateral direction. The semiconductor device includes a first metal pad, a second metal pad, a third metal pad, and a fourth metal pad. The first and second metal pads are disposed over ends of the first film, respectively, the second and third metal pads are disposed over ends of the second film, respectively, and the third and fourth metal pads are disposed over ends of the third film, respectively. The semiconductor device includes a first heater, a second heater, and a third heater, respectively disposed below the first film, the second film, and the third film.
    Type: Application
    Filed: April 10, 2023
    Publication date: October 10, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Pin Chang, Hung-Ju Li, Yu-Wei Ting, Kuo-Ching Huang
  • Publication number: 20240329361
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a circuit assembly. The movable assembly is configured to connect an optical element, the movable assembly is movable relative to the fixed assembly, and the optical element has an optical axis. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The circuit assembly includes a plurality of circuits and is affixed to the fixed assembly.
    Type: Application
    Filed: June 7, 2024
    Publication date: October 3, 2024
    Inventors: Sin-Hong LIN, Yung-Ping YANG, Wen-Yen HUANG, Yu-Cheng LIN, Kun-Shih LIN, Chao-Chang HU, Yung-Hsien YEH, Mao-Kuo HSU, Chih-Wei WENG, Ching-Chieh HUANG, Chih-Shiang WU, Chun-Chia LIAO, Chia-Yu CHANG, Hung-Ping CHEN, Wei-Zhong LUO, Wen-Chang LIN, Shou-Jen LIU, Shao-Chung CHANG, Chen-Hsin HUANG, Meng-Ting LIN, Yen-Cheng CHEN, I-Mei HUANG, Yun-Fei WANG, Wei-Jhe SHEN
  • Patent number: 12101931
    Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: September 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Tuo Huang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Yu-Ling Hsu, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
  • Publication number: 20240290629
    Abstract: A method for CMP includes following operations. A first metal layer and a second metal layer are formed in a dielectric structure. The second metal layer is formed over a portion of the first metal layer. A first composition is provided to remove a portion of the first metal layer. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed to expose the second metal layer. A CMP operation is performed to remove a portion of the first metal layer, a portion of the second metal layer and a portion of the dielectric structure.
    Type: Application
    Filed: April 29, 2024
    Publication date: August 29, 2024
    Inventors: JI CUI, FU-MING HUANG, TING-KUI CHANG, TANG-KUEI CHANG, CHUN-CHIEH LIN, WEI-WEI LIANG, LIANG-GUANG CHEN, KEI-WEI CHEN, HUNG YEN, TING-HSUN CHANG, CHI-HSIANG SHEN, LI-CHIEH WU, CHI-JEN LIU
  • Patent number: 12068032
    Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Kuang Yang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair, Chia-Sheng Lin
  • Patent number: 12068271
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Grant
    Filed: July 23, 2023
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chi Chen, Hsun-Ying Huang, Chih-Ming Lee, Shang-Yen Wu, Chih-An Yang, Hung-Wei Ho, Chao-Ching Chang, Tsung-Wei Huang
  • Publication number: 20240273675
    Abstract: An image calibration method is applied to an image calibration device includes an image receiver and an operation processor. The image calibration method of providing a motion deblur function includes driving a first camera to capture a first image having a first exposure time, driving a second camera disposed adjacent to the first camera to capture a second image having a second exposure time different from and at least partly overlapped with the first exposure time, and fusing a first feature of the first image and a second feature of the second image to generate a fusion image.
    Type: Application
    Filed: January 2, 2024
    Publication date: August 15, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Hua Huang, Pin-Wei Chen, Keh-Tsong Li, Shao-Yang Wang, Chia-Hui Kuo, Hung-Chih Ko, Yun-I Chou, Yen-Yang Chou, Chien-Ho Yu, Chi-Cheng Ju, Ying-Jui Chen
  • Publication number: 20240276893
    Abstract: Phase change material (PCM) switches and methods of fabrication thereof that include a phase change material layer and a selector having a first electrode and an ovonic threshold switching (OTS) material layer. The first electrode may selectively apply a bias voltage to the OTS layer, causing localized heating within the OTS layer. The phase change material layer may be in thermal contact with the OTS layer such that the OTS layer may heat an active region of the phase change material layer. By controlling the voltage applied to the first electrode and the resultant heating within the OTS layer, the active region of the phase change material layer may be selectively transitioned between a high resistivity state and a low resistivity state. A PCM switch according to various embodiments may enable low power and fast switching between high resistivity and low resistivity states and reduced parasitic capacitance.
    Type: Application
    Filed: June 1, 2023
    Publication date: August 15, 2024
    Inventors: Hung-Ju Li, Kuo-Ching Huang, Yu-Wei Ting, Kuo-Pin Chang
  • Patent number: 12057397
    Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: August 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuen-Shin Liang, Chun-I Tsai, Chih-Wei Chang, Chun-Hsien Huang, Hung-Yi Huang, Keng-Chu Lin, Ken-Yu Chang, Sung-Li Wang, Chia-Hung Chu, Hsu-Kai Chang
  • Patent number: 12057495
    Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Sheng Huang, Hung-Chang Sun, I-Ming Chang, Zi-Wei Fang
  • Patent number: 10682815
    Abstract: A stereolithography 3D (three-dimensional) printer and a method of adjusting temperature of printing materials thereof are provided. The stereolithography 3D printer has a material tank for accommodating print materials, a light module, a temperature-adjusting module, a temperature-sensing module, and a curing platform. The stereolithography 3D printer executes a procedure of controlling temperature for adjusting a temperature of the print material if a sensed temperature doesn't reach a default value, and executes a procedure of 3D printing for manufacturing a 3D physical model by using the print material whose temperature had been adjusted. The printing quality of the 3D physical models can be effectively improved via controlling the temperature of the print materials.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: June 16, 2020
    Assignees: XYZPRINTING, INC., KINPO ELECTRONICS, INC.
    Inventors: Chung-Yen Gir, Hung-Wei Huang, Tsung-Hua Kuo
  • Publication number: 20190389132
    Abstract: A stereolithography 3D printer (1) and a method of adjusting temperature of printing materials thereof are provided. The stereolithography 3D printer (1) has a material tank (105) for accommodating print materials (20), a light module (103), a temperature-adjusting module (101), a temperature-sensing module (102), and a curing platform (104). The stereolithography 3D printer (1) executes a procedure of controlling temperature for adjusting a temperature of the print materials (20) if a sensed temperature doesn't reach a default value, and executes a procedure of 3D printing for manufacturing a 3D physical model by using the print materials (20) whose temperature had been adjusted. The printing quality of the 3D physical models can be effectively improved via controlling the temperature of the print materials (20).
    Type: Application
    Filed: January 25, 2019
    Publication date: December 26, 2019
    Inventors: Chung-Yen GIR, Hung-Wei HUANG, Tsung-Hua KUO
  • Publication number: 20080290783
    Abstract: The present invention discloses a self-assembled monolayer with a general formula G1-R-G2, wherein G1 is SH. R of the mentioned general formula comprises one or any combination selected from the group consisting of the following: unsubstituted linear, branched, or cyclic alkyl moiety; single or multi-substituted linear, branched, or cyclic alkyl moiety with substituent selected from the group consisting of alkene and alkyne; aromatic group; multiple fused ring group; and multiple fused ring group with heteroatoms. G2 is an electron-withdrawing group.
    Type: Application
    Filed: May 25, 2007
    Publication date: November 27, 2008
    Inventors: Yu-Tai Tao, Kun-Yang Wu, Ming-Chin Hung, Hung-Wei Huang