Abstract: Circuits and techniques are described for high-speed transceivers (e.g., repeaters such as re-drivers or re-timers) that ensure that the instantaneous voltage at an input or output of a connected device remains within a desired or specified voltage range.

Abstract: Circuits and techniques are described for high-speed transceivers (e.g., repeaters such as re-drivers or re-timers) that ensure that the instantaneous voltage at an input or output of a connected device remains within a desired or specified voltage range.

Abstract: An in-situ unplug detector circuit detects when a cable is disconnected or unplugged. Detection does not have to wait for normal signaling to pause, such at the end of a frame or timeout. Instead, detection occurs during normal signaling. When the cable is disconnected, the transmitter no longer drives the load at the far end of the cable, and thus can drive the near end to a higher high voltage and to a lower low voltage. The increased voltage swing is detected by a detector at the near end that amplifies the transmitter output to the cable. A fast detector has a higher bandwidth and faster response time than a slow detector, and generates a fast detect signal that crosses over a slow detect signal. When the cable is disconnected, the fast detect signal again crosses over the slow detect signal, and decision logic activates an unplug signal.

Abstract: Distortions of both amplitude and phase along a transmission line are compensated for by a trace canceller inserted between a transmitter and a receiver. The trace canceller has an equalizer that compensates for a trace length between the transmitter and the trace canceller. A variable gain amplifier between the equalizer and an output buffer has its gain controlled by an automatic gain control circuit that compares low-frequency swings of the input and output of the trace canceller. The gain of the variable gain amplifier is reduced to prevent the output buffer from saturating and clipping peak voltages on its output. Thus both the variable gain amplifier and the output buffer remain in the linear region. Training pulses from the transmitter are passed through the trace canceller without clipping of peak voltages, allowing the transmitter and receiver to adjust transmission parameters to best match the transmission line.

Abstract: Distortions of both amplitude and phase along a transmission line are compensated for by a trace canceller inserted between a transmitter and a receiver. The trace canceller has an equalizer that compensates for a trace length between the transmitter and the trace canceller. A variable gain amplifier between the equalizer and an output buffer has its gain controlled by an automatic gain control circuit that compares low-frequency swings of the input and output of the trace canceller. The gain of the variable gain amplifier is reduced to prevent the output buffer from saturating and clipping peak voltages on its output. Thus both the variable gain amplifier and the output buffer remain in the linear region. Training pulses from the transmitter are passed through the trace canceller without clipping of peak voltages, allowing the transmitter and receiver to adjust transmission parameters to best match the transmission line.

Abstract: Distortions of both amplitude and phase along a transmission line are compensated for by a trace canceller inserted between a transmitter and a receiver. The trace canceller has an equalizer that compensates for a trace length between the transmitter and the trace canceller. A variable gain amplifier between the equalizer and an output buffer has its gain controlled by an automatic gain control circuit that compares low-frequency swings of the input and output of the trace canceller. The gain of the variable gain amplifier is reduced to prevent the output buffer from saturating and clipping peak voltages on its output. Thus both the variable gain amplifier and the output buffer remain in the linear region. Training pulses from the transmitter are passed through the trace canceller without clipping of peak voltages, allowing the transmitter and receiver to adjust transmission parameters to best match the transmission line.

Abstract: An in-situ unplug detector circuit detects when a cable is disconnected or unplugged. Detection does not have to wait for normal signaling to pause, such at the end of a frame or timeout. Instead, detection occurs during normal signaling. When the cable is disconnected, the transmitter no longer drives the load at the far end of the cable, and thus can drive the near end to a higher high voltage and to a lower low voltage. The increased voltage swing is detected by a detector at the near end that amplifies the transmitter output to the cable. A fast detector has a higher bandwidth and faster response time than a slow detector, and generates a fast detect signal that crosses over a slow detect signal. When the cable is disconnected, the fast detect signal again crosses over the slow detect signal, and decision logic activates an unplug signal.

Abstract: Disclosed are embodiments for an intermediary signal conditioning device with an input adaptable detection mode. In one embodiment, an intermediary signal conditioning device has a control module, an input module, and an output module. The input module and the control module are for receiving an input signal. The control module is configured to interrupt the output module within a duration of time to allow at least a minimum pulse length of the input signal to be output as an output signal from the output module. The intermediary signal conditioning device is configured to condition the input signal for retransmission as the output signal.

Abstract: An in-situ unplug detector circuit detects when a cable is disconnected or unplugged. Detection does not have to wait for normal signaling to pause, such at the end of a frame or timeout. Instead, detection occurs during normal signaling. When the cable is disconnected, the transmitter no longer drives the load at the far end of the cable, and thus can drive the near end to a higher high voltage and to a lower low voltage. The increased voltage swing is detected by a detector at the near end that amplifies the transmitter output to the cable. A fast detector has a higher bandwidth and faster response time than a slow detector, and generates a fast detect signal that crosses over a slow detect signal. When the cable is disconnected, the fast detect signal again crosses over the slow detect signal, and decision logic activates an unplug signal.

Abstract: Distortions of both amplitude and phase along a transmission line are compensated for by a trace canceller inserted between a transmitter and a receiver. The trace canceller has an equalizer that compensates for a trace length between the transmitter and the trace canceller. A variable gain amplifier between the equalizer and an output buffer has its gain controlled by an automatic gain control circuit that compares low-frequency swings of the input and output of the trace canceller. The gain of the variable gain amplifier is reduced to prevent the output buffer from saturating and clipping peak voltages on its output. Thus both the variable gain amplifier and the output buffer remain in the linear region. Training pulses from the transmitter are passed through the trace canceller without clipping of peak voltages, allowing the transmitter and receiver to adjust transmission parameters to best match the transmission line.

Abstract: Distortions of both amplitude and phase along a transmission line are compensated for by a trace canceller inserted between a transmitter and a receiver. The trace canceller has an equalizer that compensates for a trace length between the transmitter and the trace canceller. A variable gain amplifier between the equalizer and an output buffer has its gain controlled by an automatic gain control circuit that compares low-frequency swings of the input and output of the trace canceller. The gain of the variable gain amplifier is reduced to prevent the output buffer from saturating and clipping peak voltages on its output. Thus both the variable gain amplifier and the output buffer remain in the linear region. Training pulses from the transmitter are passed through the trace canceller without clipping of peak voltages, allowing the transmitter and receiver to adjust transmission parameters to best match the transmission line.

Abstract: An in-situ unplug detector circuit detects when a cable is disconnected or unplugged. Detection does not have to wait for normal signaling to pause, such at the end of a frame or timeout. Instead, detection occurs during normal signaling. When the cable is disconnected, the transmitter no longer drives the load at the far end of the cable, and thus can drive the near end to a higher high voltage and to a lower low voltage. The increased voltage swing is detected by a detector at the near end that amplifies the transmitter output to the cable. A fast detector has a higher bandwidth and faster response time than a slow detector, and generates a fast detect signal that crosses over a slow detect signal. When the cable is disconnected, the fast detect signal again crosses over the slow detect signal, and decision logic activates an unplug signal.

Abstract: Distortions of both amplitude and phase along a transmission line are compensated for by a trace canceller inserted between a transmitter and a receiver. The trace canceller has an equalizer that compensates for a trace length between the transmitter and the trace canceller. A variable gain amplifier between the equalizer and an output buffer has its gain controlled by an automatic gain control circuit that compares low-frequency swings of the input and output of the trace canceller. The gain of the variable gain amplifier is reduced to prevent the output buffer from saturating and clipping peak voltages on its output. Thus both the variable gain amplifier and the output buffer remain in the linear region. Training pulses from the transmitter are passed through the trace canceller without clipping of peak voltages, allowing the transmitter and receiver to adjust transmission parameters to best match the transmission line.

Abstract: Power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is equalized by an equalizer and then applied to a multiplier and smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too small. The reference voltage compared can be generated by an equalizer, multiplier, and low-pass filter to match process, temperature, and supply-voltage variations in the primary signal path. The multipliers can be implemented with Gilbert cells. The equalizers can receive control signals to control attenuation of different frequency components.

Abstract: Power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is equalized by an equalizer and then applied to a multiplier and smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too small. The reference voltage compared can be generated by an equalizer, multiplier, and low-pass filter to match process, temperature, and supply-voltage variations in the primary signal path. The multipliers can be implemented with Gilbert cells. The equalizers can receive control signals to control attenuation of different frequency components.

Abstract: A clock generator corrects the duty cycle of an input clock. The input clock has a poor duty cycle such as less than 50%. The input clock is applied to a phase detector of a phase-locked loop (PLL). A voltage-controlled oscillator (VCO) of the PLL drives a feedback clock that is also applied to the phase detector. An edge-triggered set-reset SR flip-flop generates a duty-cycle-corrected output clock. The SR flip-flop is set by the leading edge of the input clock, but is reset by the trailing edge of the feedback clock. The VCO generates the feedback clock with the desired duty cycle, such as 50%. The leading edge of the output clock is generated by the input clock, avoiding noise generated by the PLL, while the trailing edge of the output clock is generated by the feedback clock and has PLL noise, but corrects for the desired duty cycle.

Abstract: A power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is applied to a multiplier, which generates a squared difference. The squared difference is smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage, either explicitly or implicitly, to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too small. The multiplier can be implemented with a Gilbert cell, while a filter-comparator converts the differential Gilbert-cell output to a single-ended signal and filters the signal. The reference voltage compared can be set by the switching threshold of the filter comparator or other logic gates. A complementary Gilbert cell and filter-comparator can be used to increase the operating range.

Abstract: When the clock is stopped during a power-down mode, a clock duty-cycle detector asserts a power-down signal. The clock input is filtered to produce an average clock voltage over several clock periods. The average clock voltage is compared to an upper reference voltage to determine when the clock's duty cycle (high pulse-width percent) is above an upper limit. The average clock voltage is also compared to a lower reference voltage to determine when the clock's duty cycle is below a lower limit. When the clock's duty cycle is above the upper limit or below the lower limit the power-down signal is activated by logic. The logic disables the power-down signal when the clock's duty cycle is between the upper and lower limits. High-frequency clock glitches do not falsely trigger a power-up, since glitches are usually narrow and not sufficiently wide to reach the lower limit.