Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a redistribution layer (RDL) module, a first semiconductor module, an interconnection module, a second semiconductor module and a molding material. The first semiconductor module is disposed on the RDL module. The interconnection module is disposed on the RDL module. The second semiconductor module is disposed on the interconnection module. The molding material covers the RDL module and surrounds the first semiconductor module and the second semiconductor module. A top surface of the first semiconductor module and a top surface of the second semiconductor module are exposed by the molding material.

Abstract: A head-mounted display includes a display device, a connecting structure and a head abutting portion. The connecting structure is in a shape of strip. The connecting structure has two opposite ends. The ends are respectively connected with the display device. The connecting structure and the display device define an accommodation space. The accommodation space is configured to accommodate a head of a user. The head abutting portion is pivotally connected with the connecting structure. The head abutting portion is at least partially located between the connecting structure and the display device. The head abutting portion is configured to abut against the head of the user.

Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: A package structure including a first die, a second die, an encapsulant, a dam structure, a light-transmitting sheet, a conductive connector, a circuit layer, and a conductive terminal is provided. The first die includes a first active surface. The first active surface has a sensing area. The second die is arranged such that a second back surface thereof faces the first die. The encapsulant covers the second die. The encapsulant has a first encapsulating surface and a second encapsulating surface. The dam structure is located on the first encapsulating surface and exposes the sensing area. The light-transmitting sheet is located on the dam structure. The conductive connector penetrates the encapsulant. The circuit layer is located on the second encapsulating surface. The first die is electrically connected to the second die through the conductive connector and the circuit layer. The conductive terminal is disposed on the circuit layer.

Abstract: A management circuit is coupled to multiple processor cores for performing current suppression. The management circuit includes a detection circuit and a throttle signal generator. The detection circuit is operative to receive an activity signal from each processor core, and estimate a total current consumed by the plurality of processor cores based on activity signals. The activity signal indicates a current index proportional to current consumption of the processor core in a given time period. The throttle signal generator is operative to assert or de-assert throttle signals to the processor cores, one processor core at a time, based on one or more metrics calculated from the total current.

Abstract: A projection apparatus including a projection device, a reflecting component, and an image capturing device is provided. The projection device is adapted to project an image light beam to form a projection image. The reflecting component is disposed on the projection device and has a reflecting surface. The image capturing device is disposed on the projection device and has an image capturing end. The image capturing end faces the reflecting surface. The reflecting surface is adapted to reflect the projection image to the image capturing end.

Abstract: A magnetic tunnel junction device includes a pillar structure including, from bottom to top, a bottom electrode and a magnetic tunnel junction structure, a top electrode overlying the magnetic tunnel junction structure, and a dielectric metal oxide layer extending from a sidewall of the pillar structure to a sidewall of the top electrode. The magnetic tunnel junction structure contains a reference magnetization layer including a first ferromagnetic material, a tunnel barrier layer, and a free magnetization layer including a second ferromagnetic material. The top electrode includes a metallic material containing a nonmagnetic metal element. The dielectric metal oxide layer may be formed by performing an oxidation process that oxidizes a residual metal film after a focused ion beam etch process, and eliminates conductive paths from surfaces of the pillar structure.

Abstract: A package structure including a first die, a second die, a dielectric body, a conductive terminal, a circuit layer and a patterned insulating layer is provided. The second die is disposed on the first die. A second active surface of the second die faces a first active surface of the first die. The dielectric body covers the first die. The conductive terminal is disposed on the dielectric body and opposite to the second die. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first die is electrically connected to the conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body. The second die is electrically connected to the first die through the second circuit portion. The patterned insulating layer covers the circuit layer and is embedded in the dielectric body.

Abstract: A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.

Abstract: A p-aminobenzoic acid-producing microorganism is provided. The p-aminobenzoic acid-producing microorganism is obtained by a method for preparing a p-aminobenzoic acid-producing microorganism. The method for preparing a p-aminobenzoic acid-producing microorganism includes (a) performing an acclimation process on a source microorganism with at least one sulfonamide antibiotic to obtain at least one acclimatized microorganism and (b) screening out at least one p-aminobenzoic acid-producing microorganism from the at least one acclimatized microorganism, wherein the at least one p-aminobenzoic acid-producing microorganism has a higher p-aminobenzoic acid titer than the source microorganism.

Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: A packaging structure including first, second, and third dies, an encapsulant, a circuit structure, and a filler is provided. The encapsulant covers the first die. The circuit structure is disposed on the encapsulant. The second die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die has an optical signal transmission area. The filler is disposed between the second die and the circuit structure and between the third die and the circuit structure. A groove is present on an upper surface of the circuit structure. The upper surface includes first and second areas located on opposite sides of the groove. The filler directly contacts the first area. The filler is away from the second area. A manufacturing method of a packaging structure is also provided.

Abstract: Improved methods of patterning magnetic tunnel junctions (MTJs) for magnetoresistive random-access memory (MRAM) and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes depositing a bottom electrode layer over a semiconductor substrate; depositing an MTJ film stack over the bottom electrode layer; depositing a top electrode layer over the MTJ film stack; patterning the top electrode layer; performing a first etch process to pattern the MTJ film stack; performing a first trim process on the MTJ film stack; after performing the first trim process, depositing a first spacer layer over the MTJ film stack; and after depositing the first spacer layer, performing a second etch process to pattern the first spacer layer, the MTJ film stack, and the bottom electrode layer to form an MRAM cell.

Abstract: A magnetic tunnel junction device includes a pillar structure including, from bottom to top, a bottom electrode and a magnetic tunnel junction structure, a top electrode overlying the magnetic tunnel junction structure, and a dielectric metal oxide layer extending from a sidewall of the pillar structure to a sidewall of the top electrode. The magnetic tunnel junction structure contains a reference magnetization layer including a first ferromagnetic material, a tunnel barrier layer, and a free magnetization layer including a second ferromagnetic material. The top electrode includes a metallic material containing a nonmagnetic metal element. The dielectric metal oxide layer may be formed by performing an oxidation process that oxidizes a residual metal film after a focused ion beam etch process, and eliminates conductive paths from surfaces of the pillar structure.

Abstract: A charge pump drive circuit is disclosed. The charge pump drive circuit provides a switch signal to a charge pump which provides a memory with a read voltage and a read current. The charge pump drive circuit includes a read drive circuit and a standby drive circuit. The read drive circuit is powered by a first power supply and provides the charge pump with a switch signal when the memory is in an active reading state. The standby drive circuit is powered by a second power supply and provides the charge pump with a switch signal when the memory is in a read standby state. The first power supply provides a voltage level ranging from 1.6 V to 3.8 V, and the second power supply provides a voltage level of 1.5 V.

Abstract: A charge pump drive circuit is disclosed. The charge pump drive circuit provides a switch signal to a charge pump which provides a memory with a read voltage and a read current. The charge pump drive circuit includes a read drive circuit and a standby drive circuit. The read drive circuit is powered by a first power supply and provides the charge pump with a switch signal when the memory is in an active reading state. The standby drive circuit is powered by a second power supply and provides the charge pump with a switch signal when the memory is in a read standby state. The first power supply provides a voltage level ranging from 1.6 V to 3.8 V, and the second power supply provides a voltage level of 1.5 V.