Abstract: A method of manufacturing a hybrid random access memory in a system-on-chip, including steps of providing a semiconductor substrate with a magnetoresistive random access memory (MRAM) region and a resistive random-access memory (ReRAM) region, forming multiple ReRAM cells in the ReRAM region on the semiconductor substrate, forming a first dielectric layer on the semiconductor substrate, wherein the ReRAM cells are in the first dielectric layer, forming multiple MRAM cells in the MRAM region on the first dielectric layer, and forming a second dielectric layer on the first dielectric layer, wherein the MRAM cells are in the second dielectric layer.

Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

Abstract: The present invention provides a scan driver and a display using the same. The scan driver includes multiple stages of driving units. The driving units are controlled by a start signal, a clock signal and at least one selection signal. The ith stage of the driving unit includes a shift register and a de-multiplexer. The shift register generates a scan signal according to the clock signal and a trigger signal. The de-multiplexer selectively outputs the scan signal to multiple scan lines according to the at least one selection signal. The trigger signal of the 1st stage of the driving unit is the start signal, and the trigger signal of the (i+1)th stage of the driving unit is the scan signal of the ith stage of the driving unit.

Abstract: The present invention provides a scan driver and a display using the same. The scan driver includes multiple stages of driving units. The driving units are controlled by a start signal, a clock signal and at least one selection signal. The ith stage of the driving unit includes a shift register and a de-multiplexer. The shift register generates a scan signal according to the clock signal and a trigger signal. The de-multiplexer selectively outputs the scan signal to multiple scan lines according to the at least one selection signal. The trigger signal of the 1st stage of the driving unit is the start signal, and the trigger signal of the (i+1)th stage of the driving unit is the scan signal of the ith stage of the driving unit.

Abstract: An OLED display device and a driving method thereof are disclosed. The display device includes a display panel, m scan lines, n first control lines, n second control lines and a compensation driving circuit. The display panel includes a plurality of pixel units. Each of the pixel units has a compensation circuit. The pixel units are arranged into m rows, and pixel units of the rows are divided into n groups. The scan lines are disposed corresponding to and electrically connected with the pixel units of the rows. The first control lines and the second control lines are disposed corresponding to the groups and electrically connected with the pixel units of the corresponding groups. The ratio (m/n) is a positive integer, and 2?(m/n)<m. The compensation driving circuit is electrically connected with the pixel units through the scan lines, the first control lines and the second control lines.

Abstract: A pixel structure, a display panel, a display and a driving method thereof are disclosed. The pixel structure comprises an organic light emitting diode, a driving transistor, a storage capacitance, and a switch transistor. A first terminal of the driving transistor receives an image retention cancellation signal. The image retention cancellation signal changes to a second level from a first level before the driving transistor drives the organic light emitting diode so that the driving transistor is operated in a forward curve. A second terminal of the driving transistor is coupled to the light emitting diode. One terminal of the storage capacitance receives a common voltage, and the other terminal of the storage capacitance is coupled to a control terminal of the driving transistor. The switch transistor is controlled by a scan signal to output a data signal to the control terminal of the driving transistor.