Patents by Inventor Huojin Tu
Huojin Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230332328Abstract: The present application provides a reaction device for improving epitaxial growth uniformity, provided with a main inject port on one side and an exhaust port on the other side, wherein a base is provided between the main inject port and the exhaust port; the reaction cavity is provided with first and second inject pipes; the length directions of the first and second inject pipes are perpendicular to a connecting line between the main inject port and the exhaust port; the lengths of the first and second inject pipes are both equal to the radius of the base; the first and second inject pipes are located in a straight line along the length directions; the first and second inject pipes are each provided with a plurality of holes; and the plurality of holes on the first and second inject pipes are located above the wafer placed on the base.Type: ApplicationFiled: March 24, 2023Publication date: October 19, 2023Applicant: Shanghai Huali Integrated Circuit CorporationInventors: Hui Wang, Huojin Tu, Jiaqi Hong, Jun Tan, Jingxun Fang
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Patent number: 11495502Abstract: The disclosure provides a manufacturing method for a fin field-effect transistor. The method to make the fin field-effect transistor comprises: forming a fin structure and a gate structure spanning on the fin structure on a substrate; and forming a source-drain region on the fin structure, which comprises: forming an epitaxial layer; and forming a sacrificial layer on the surface of the epitaxial layer to prevent the epitaxial layer from being lost in the subsequent removal steps.Type: GrantFiled: March 16, 2021Date of Patent: November 8, 2022Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATIONInventors: Huojin Tu, Jueyang Liu, Zhanyuan Hu
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Patent number: 11476114Abstract: An epitaxial growth process for a semiconductor device includes providing a semiconductor substrate, forming a plurality of Dummy Gate structures on the surface of the semiconductor substrate, and forming grooves in a self-aligned manner on both sides of the Dummy Gate structures; forming an initial seed layer on the inner side surfaces of the grooves, the thickness of the formed initial seed layer on the bottoms of the grooves being greater and the thickness of the formed initial seed layer on the sidewalls being smaller since the growth speed of crystal faces <100> and <110> is different; longitudinally etching the initial seed layer to thin the bottom of the initial seed layer to form a seed layer; forming a main body layer on the seed layer, the main body layer filling the grooves; and forming a cover layer on the main body layer.Type: GrantFiled: January 5, 2021Date of Patent: October 18, 2022Assignee: Shanghai Huali Integrated Circuit CorporationInventors: Huojin Tu, Qin Deng, Jueyang Liu, Zhanyuan Hu
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Publication number: 20220102145Abstract: The present application discloses a method for forming a recess, which comprises the following steps: step 1: performing a dry etching process to a silicon substrate to form a U-shaped or ball-shaped recess; step 2: performing second etching to the recess by introducing HCl and GeH4 reaction gases in an epitaxial process chamber to form diamond-shaped recess. The present application further discloses a method for forming a recess and filling the recess with an epitaxial layer in situ. The disclosed etching changes U-shaped or ball-shaped reaction recess diamond-shaped recess by including reaction gases in the epitaxial process chamber, which is conducive to realizing the in-situ epitaxial filling process. This method reduces steps in the process loop of forming embedded epitaxial layer, thus decreasing defects from the process.Type: ApplicationFiled: January 26, 2021Publication date: March 31, 2022Inventors: Yaozeng WANG, Yincheng Zheng, Wangxin Nie, Huojin Tu, Jueyang Liu, Zhanyuan Hu
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Publication number: 20210398805Abstract: An epitaxial growth process for a semiconductor device includes providing a semiconductor substrate, forming a plurality of Dummy Gate structures on the surface of the semiconductor substrate, and forming grooves in a self-aligned manner on both sides of the Dummy Gate structures; forming an initial seed layer on the inner side surfaces of the grooves, the thickness of the formed initial seed layer on the bottoms of the grooves being greater and the thickness of the formed initial seed layer on the sidewalls being smaller since the growth speed of crystal faces <100> and <110> is different; longitudinally etching the initial seed layer to thin the bottom of the initial seed layer to form a seed layer; forming a main body layer on the seed layer, the main body layer filling the grooves; and forming a cover layer on the main body layer.Type: ApplicationFiled: January 5, 2021Publication date: December 23, 2021Applicant: Shanghai Huali Integrated Circuit CorporationInventors: Huojin Tu, Qin Deng, Jueyang Liu, Zhanyuan Hu
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Publication number: 20210375696Abstract: The disclosure provides a manufacturing method for a fin field-effect transistor. The method to make the fin field-effect transistor comprises: forming a fin structure and a gate structure spanning on the fin structure on a substrate; and forming a source-drain region on the fin structure, which comprises: forming an epitaxial layer; and forming a sacrificial layer on the surface of the epitaxial layer to prevent the epitaxial layer from being lost in the subsequent removal steps.Type: ApplicationFiled: March 16, 2021Publication date: December 2, 2021Inventors: Huojin TU, Jueyang Liu, Zhanyuan Hu
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Patent number: 9741824Abstract: The present disclosure provides a method for forming a semiconductor device. The method includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and forming trenches in the semiconductor substrate on both sides of the gate structure. The method also includes forming a stress layer on inner sidewalls of each trench to fill up the trench; forming an interlayer on the stress layer, and forming a capping layer on the interlayer, wherein a top surface of the capping layer is higher than a top surface of the semiconductor substrate, and a lattice mismatch between the interlayer and the capping layer is lower than a lattice mismatch between the capping layer and the stress layer.Type: GrantFiled: August 18, 2015Date of Patent: August 22, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: Huojin Tu
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Publication number: 20160064522Abstract: The present disclosure provides a method for forming a semiconductor device. The method includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and forming trenches in the semiconductor substrate on both sides of the gate structure. The method also includes forming a stress layer on inner sidewalls of each trench to fill up the trench; forming an interlayer on the stress layer, and forming a capping layer on the interlayer, wherein a top surface of the capping layer is higher than a top surface of the semiconductor substrate, and a lattice mismatch between the interlayer and the capping layer is lower than a lattice mismatch between the capping layer and the stress layer.Type: ApplicationFiled: August 18, 2015Publication date: March 3, 2016Inventor: HUOJIN TU
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Patent number: 8951852Abstract: The disclosure involves a semiconductor device and a manufacturing method thereof. First, a dielectric layer and a stack comprising a Si layer and at least one SiGe layer located on the Si layer are formed in sequence on a substrate. Then the stack and the dielectric layer are patterned to form a dummy gate and a gate dielectric layer, respectively. Next, sidewall spacers are formed on opposite sides of the dummy gate, and source and drain regions with embedded SiGe are formed. Then, the dummy gate is removed to form an opening, in which a gate material such as metal is filled. In RMG techniques, by adopting the stack consisting of Si and SiGe layers as a dummy gate, the method can further increase the compressive stress in the channel of a MOS device and thus improve carrier mobility as compared to traditional polysilicon dummy gate process.Type: GrantFiled: September 23, 2011Date of Patent: February 10, 2015Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventors: Yonggen He, Huojin Tu
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Patent number: 8912568Abstract: A semiconductor device and manufacturing method therefor includes a ?-shaped embedded source or drain regions. A U-shaped recess is formed in a Si substrate using dry etching and a SiGe layer is grown epitaxially on the bottom of the U-shaped recess. Using an orientation selective etchant having a higher etching rate with respect to Si than SiGe, wet etching is performed on the Si substrate sidewalls of the U-shaped recess, to form a ?-shaped recess.Type: GrantFiled: January 19, 2012Date of Patent: December 16, 2014Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventors: Huanxin Liu, Huojin Tu
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Patent number: 8610175Abstract: This invention relates to a semiconductor device and a manufacturing method thereof for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom, a SiGe seed layer is formed on sidewalls of the recess and a second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.Type: GrantFiled: December 9, 2011Date of Patent: December 17, 2013Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventors: Zhongshan Hong, Huojin Tu
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Patent number: 8587026Abstract: This invention relates to a semiconductor device and a manufacturing method therefor for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A SiGe seed layer is formed on sidewalls of the recess, and a first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom. A second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer, and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.Type: GrantFiled: December 7, 2011Date of Patent: November 19, 2013Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventors: Yonggen He, Huojin Tu, Jing Lin
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Publication number: 20130037856Abstract: This invention relates to a semiconductor device and a manufacturing method therefor for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A SiGe seed layer is formed on sidewalls of the recess, and a first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom. A second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer, and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.Type: ApplicationFiled: December 7, 2011Publication date: February 14, 2013Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Yonggen He, Huojin Tu, Jing Lin
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Publication number: 20130037858Abstract: This invention relates to a semiconductor device and a manufacturing method thereof for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom, a SiGe seed layer is formed on sidewalls of the recess and a second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.Type: ApplicationFiled: December 9, 2011Publication date: February 14, 2013Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: ZHONGSHAN HONG, Huojin Tu
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Publication number: 20120319120Abstract: The disclosure involves a semiconductor device and a manufacturing method thereof. First, a dielectric layer and a stack comprising a Si layer and at least one SiGe layer located on the Si layer are formed in sequence on a substrate. Then the stack and the dielectric layer are patterned to form a dummy gate and a gate dielectric layer, respectively. Next, sidewall spacers are formed on opposite sides of the dummy gate, and source and drain regions with embedded SiGe are formed. Then, the dummy gate is removed to form an opening, in which a gate material such as metal is filled. In RMG techniques, by adopting the stack consisting of Si and SiGe layers as a dummy gate, the method can further increase the compressive stress in the channel of a MOS device and thus improve carrier mobility as compared to traditional polysilicon dummy gate process.Type: ApplicationFiled: September 23, 2011Publication date: December 20, 2012Applicant: Semiconductor Manufacturing International (Beijing) CorporationInventors: YONGGEN HE, Huojin Tu
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Publication number: 20120319168Abstract: A semiconductor device and manufacturing method therefor includes a ?-shaped embedded source or drain regions. A U-shaped recess is formed in a Si substrate using dry etching and a SiGe layer is grown epitaxially on the bottom of the U-shaped recess. Using an orientation selective etchant having a higher etching rate with respect to Si than SiGe, wet etching is performed on the Si substrate sidewalls of the U-shaped recess, to form a ?-shaped recess.Type: ApplicationFiled: January 19, 2012Publication date: December 20, 2012Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Huanxin Liu, Huojin Tu