Abstract: In a processor, an instruction unit that issues a plurality of instructions is coupled to a mapping unit. Each instruction contains at least one "virtual" address corresponding to a user-addressable register as defined by an instruction set architecture. A register file having a number of physical register addresses in excess of the user addressable virtual register address is also coupled to the mapping unit. The mapping unit receives instructions from the instruction unit and generates a map value for each virtual register address. The mapping unit also maintains a status value for each physical register address. Maintaining the status value provides for out-of-order completion and in-order retirement. A new mapping is generated each time a virtual register address is used as a destination register address of an instruction. This insures that no physical register address will be overwritten before all older instructions have been resolved.