Abstract: A semiconductor device manufacturing method, wherein the etching apparatus used includes a sample loading chamber (15), a vacuum transition chamber (14), a reactive ion plasma etching chamber (10), an ion beam etching chamber (11), a film coating chamber (12), and a vacuum transport chamber (13). Without interrupting the vacuum, reactive ion etching is first adopted to etch to an isolation layer (102); then, ion beam etching is performed to etch into a fixed layer (101) and stopped near a bottom electrode metal layer (100), leaving only a small amount of the fixed layer (101); subsequently, reactive ion etching is adopted to etch to the bottom electrode metal layer (100); and finally, ion beam cleaning is performed to remove metal residues and sample surface treatment, and coating protection is performed.

Abstract: Disclosed is a method for manufacturing a magnetic tunnel junction, using an etching apparatus including a sample loading chamber, a vacuum transition chamber, a reactive ion plasma etching chamber, an ion beam etching chamber, a coating chamber and a vacuum transmission chamber, wherein a magnetic tunnel junction is etched, cleaned and coated for protection without interrupting a vacuum by using the reactive ion plasma etching chamber, the ion beam etching chamber, and the coating chamber in combination. The invention can effectively reduce damages and contaminations of devices, avoid the influence caused by over-etching, and improve performance of devices; at the same time, it can accurately control the steepness of an etching pattern and obtain a pattern result that meets performance requirements.

Abstract: Disclosed is method for etching a magnetic tunnel junction. An etching apparatus used comprises a sample loading chamber, a vacuum transition chamber, a reactive ion plasma etching chamber, an ion beam etching chamber, a film coating chamber and a vacuum transport chamber. The method comprises multiple performances of the steps of reactive ion and plasma etching, ion beam etching and film coating. Multiple performances of entry into and exit from the chambers are required during the process, and the delivery between the chambers is performed under vacuum.

Abstract: A semiconductor device manufacturing method, wherein the etching apparatus used includes a sample loading chamber (15), a vacuum transition chamber (14), a reactive ion plasma etching chamber (10), an ion beam etching chamber (11), a film coating chamber (12), and a vacuum transport chamber (13). Without interrupting the vacuum, reactive ion etching is first adopted to etch to an isolation layer (102); then, ion beam etching is performed to etch into a fixed layer (101) and stopped near a bottom electrode metal layer (100), leaving only a small amount of the fixed layer (101); subsequently, reactive ion etching is adopted to etch to the bottom electrode metal layer (100); and finally, ion beam cleaning is performed to remove metal residues and sample surface treatment, and coating protection is performed.

Abstract: A method for etching magnetic tunnel junction of single isolation layer, using an etching apparatus including a sample loading chamber, a vacuum transition chamber, a reactive ion etching chamber, an ion beam etching chamber, a coating chamber, and a vacuum transmission chamber, is applicable for the reactive ion etching chamber, ion beam etching chamber and coating chamber to process and treat a wafer according to specific steps without interrupting a vacuum. It can effectively alleviate the influence of masking effect in the production process of high-density small devices.

Abstract: A multilayer magnetic tunnel junction etching method and an MRAM device. A wafer is processed according to particular steps without interrupting vacuum. A reactive ion plasma etching chamber (10) and an ion beam etching chamber (11) are used separately at least one time. The processing of a multilayer magnetic tunnel junction is always in a vacuum environment, thereby avoiding the impact of an external environment on etching. By means of the process of combining etching and cleaning, a device structure maintains good steepness, and the metal contamination and damage of a magnetic tunnel junction film structure are significantly decreased, thereby greatly increasing the performance and reliability of a device. In addition, use of both the ion beam etching chamber (11) and the reactive ion plasma etching chamber (10) solves the technical problem of an existing single etching method, and increases production efficiency and etching process precision.

Abstract: A method for monolithic integration of a hyperspectral image sensor is provided, which includes: forming a bottom reflecting layer on a surface of the photosensitive region of a CMOS image sensor wafer; forming a transparent cavity layer composed of N step structures on the bottom reflecting layer through area selective atomic layer deposition processes, where N=2m, m?1 and m is a positive integer; and forming a top reflecting layer on the transparent cavity layer. With the method, non-uniformity accumulation due to etching processes in conventional technology is minimized, and the cavity layer can be made of materials which cannot be etched. Mosaic cavity layers having such repeated structures with different heights can be formed by extending one-dimensional ASALD, such as extending in another dimension and forming repeated regions, which can be applied to snapshot hyperspectral image sensors, for example, pixels, and greatly improving performance thereof.

Abstract: A method for monolithic integration of a hyperspectral image sensor is provided, which includes: forming a bottom reflecting layer on a surface of the photosensitive region of a CMOS image sensor wafer; forming a transparent cavity layer composed of N step structures on the bottom reflecting layer through area selective atomic layer deposition processes, where N=2m, m?1 and m is a positive integer; and forming a top reflecting layer on the transparent cavity layer. With the method, non-uniformity accumulation due to etching processes in conventional technology is minimized, and the cavity layer can be made of materials which cannot be etched. Mosaic cavity layers having such repeated structures with different heights can be formed by extending one-dimensional ASALD, such as extending in another dimension and forming repeated regions, which can be applied to snapshot hyperspectral image sensors, for example, pixels, and greatly improving performance thereof.

Abstract: An apparatus and a method for epitaxially growing sources and drains of a FinFET device. The apparatus comprises: a primary chamber; a wafer-loading chamber; a transfer chamber provided with a mechanical manipulator for transferring the wafer; an etching chamber for removing a natural oxide layer on the surface of the wafer and provided with a graphite base for positioning the wafer; at least one epitaxial reaction chamber; a gas distribution device for supplying respective gases to the primary chamber, the wafer loading chamber, the transfer chamber, the etching chamber and the epitaxial reaction chamber; and a vacuum device. The wafer loading, transfer, etching, and epitaxial reaction chambers are all positioned within the primary chamber. The apparatus integrates the etching chamber and epitaxial reaction chamber to remove the natural oxide layer on the surface of the wafer in a condition of isolating water and oxygen before the epitaxial reaction has occurred.

Abstract: A semiconductor device comprises a substrate; a shallow trench isolation embedded in the substrate and forms at least one opening region; a channel region located in the opening region; a gate stack including a gate dielectric layer and a gate electrode layer, located above said channel region; a source/drain region located on both sides of the channel region, including a stress layer which provides strain for the channel region. A liner layer is provided between the shallow trench isolation and the stress layer, which serves as a crystal seed layer of the stress layer. A liner layer and a pad oxide layer are provided between the substrate and the shallow trench isolation. The liner layer is inserted between the STI and the stress layer of the source/drain region as a crystal seed layer or nucleating layer for epitaxial growth, thereby eliminating the STI edge effect during the source/drain strain engineering.