Abstract: A method and system of split-streaming direct memory access (DMA) data transfer can transfer N words of data from a source device to two different sets of memory locations using only N data read cycles and 2N data write cycles. In a single data word transfer mode, a data read operation on the memory bus is followed by two consecutive data write cycles wherein the same data is written to two different memory addresses. In a data burst mode, a data burst read operation is followed by a series of paired data write cycles, wherein in each pair of data write cycles, one of the data words is written to two different memory addresses.

Abstract: An integrated circuit having two or more power domains that include load circuits in different portions of the integrated circuit is disclosed. In order to conserve power, the circuits in one of the power domains are shut down by disconnecting the power source serving that domain. The load circuits in each power domain are buffered from the load circuits in other power domains by buffer cells. The buffer cells reduce leakage currents in the power domain that is shut down, by restricting data signals from the “live” power domain from reaching the shut-down power domain, and further by providing predetermined voltage signals to the load circuits in the shut-down power domain that are selected to minimize leakage currents in the inactive load circuits. The invention further provides a corresponding method for reducing power consumption in an integrated circuit having at least two power domains separated by a buffer cell.