Patents by Inventor Huy Minh Nguyen

Huy Minh Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11128642
    Abstract: Some embodiments of reassembly-free deep packet inspection (DPD on multicore hardware have been presented. In one embodiment, a set of packets of one or more files is received at a networked device from one or more connections. Each packet is scanned using one of a set of processing cores in the networked device without buffering the one or more files in the networked device. Furthermore, the set of processing cores may scan the packets substantially concurrently.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: September 21, 2021
    Assignee: SONICWALL INC.
    Inventors: Aleksandr Dubrovsky, John E. Gmuender, Huy Minh Nguyen, Ilya Minkin, Justin M. Brady, Boris Yanovsky
  • Patent number: 10970144
    Abstract: A method for packet processing on a multi-core processor. According to one embodiment of the invention, a first set of one or more processing cores are configured to include the capability to process packets belonging to a first set of one or more packet types, and a second set of one or more processing cores are configured to include the capability to process packets belonging to a second set of one or more packet types, where the second set of packet types is a subset of the first set of packet types. Packets belonging to the first set of packet types are processed at a processing core of either the first or second set of processing cores. Packets belonging to the second set of packet types are processed at a processing core of the first set of processing cores.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: April 6, 2021
    Assignee: SONICWALL INC.
    Inventors: John E. Gmuender, Iosif Harutyunov, Manish Mathur, Ilya Minkin, Huy Minh Nguyen
  • Publication number: 20200204568
    Abstract: Some embodiments of reassembly-free deep packet inspection (DPD on multicore hardware have been presented. In one embodiment, a set of packets of one or more files is received at a networked device from one or more connections. Each packet is scanned using one of a set of processing cores in the networked device without buffering the one or more files in the networked device. Furthermore, the set of processing cores may scan the packets substantially concurrently.
    Type: Application
    Filed: March 4, 2020
    Publication date: June 25, 2020
    Inventors: Aleksandr Dubrovsky, John E. Gmuender, Huy Minh Nguyen, Ilya Minkin, Justin M. Brady, Boris Yanovsky
  • Publication number: 20200142760
    Abstract: A method for packet processing on a multi-core processor. According to one embodiment of the invention, a first set of one or more processing cores are configured to include the capability to process packets belonging to a first set of one or more packet types, and a second set of one or more processing cores are configured to include the capability to process packets belonging to a second set of one or more packet types, where the second set of packet types is a subset of the first set of packet types. Packets belonging to the first set of packet types are processed at a processing core of either the first or second set of processing cores. Packets belonging to the second set of packet types are processed at a processing core of the first set of processing cores.
    Type: Application
    Filed: October 29, 2019
    Publication date: May 7, 2020
    Inventors: John E. Gmuender, Iosif Harutyunov, Manish Mathur, Ilya Minkin, Huy Minh Nguyen
  • Patent number: 10609043
    Abstract: Some embodiments of reassembly-free deep packet inspection (DPD on multicore hardware have been presented. In one embodiment, a set of packets of one or more files is received at a networked device from one or more connections. Each packet is scanned using one of a set of processing cores in the networked device without buffering the one or more files in the networked device. Furthermore, the set of processing cores may scan the packets substantially concurrently.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 31, 2020
    Assignee: SONICWALL INC.
    Inventors: Aleksandr Dubrovsky, John E. Gmuender, Huy Minh Nguyen, Ilya Minkin, Justin M. Brady, Boris Yanovsky
  • Patent number: 10459777
    Abstract: A method for packet processing on a multi-core processor. According to one embodiment of the invention, a first set of one or more processing cores are configured to include the capability to process packets belonging to a first set of one or more packet types, and a second set of one or more processing cores are configured to include the capability to process packets belonging to a second set of one or more packet types, where the second set of packet types is a subset of the first set of packet types. Packets belonging to the first set of packet types are processed at a processing core of either the first or second set of processing cores. Packets belonging to the second set of packet types are processed at a processing core of the first set of processing cores.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: October 29, 2019
    Assignee: SONICWALL INC.
    Inventors: John E. Gmuender, Iosif Harutyunov, Manish Mathur, Ilya Minkin, Huy Minh Nguyen
  • Patent number: 10419398
    Abstract: A method and apparatus for resource locator identifier rewrite have been presented. A security device receives from a resource host over a non-secure hypertext transfer protocol (HTTP) session a response to a request received from a client over a secure HTTP session. The response includes a uniform resource locator (URL) that is supposed to be for a resource host, but the URL does not designate a secure resource access protocol and the resource host requires the secure resource access protocol. The URL is located in the response and modified to designate the secure resource access protocol. After modification, the response is transmitted via the secure resource access protocol session to the client.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: September 17, 2019
    Assignee: SONICWALL INC.
    Inventors: John E. Gmuender, Huy Minh Nguyen, Joseph H. Levy, Michael B. Massing, Zhong Chen, David M. Telehowski
  • Publication number: 20190260766
    Abstract: Some embodiments of reassembly-free deep packet inspection (DPD on multicore hardware have been presented. In one embodiment, a set of packets of one or more files is received at a networked device from one or more connections. Each packet is scanned using one of a set of processing cores in the networked device without buffering the one or more files in the networked device. Furthermore, the set of processing cores may scan the packets substantially concurrently.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Aleksandr Dubrovsky, John E. Gmuender, Huy Minh Nguyen, Ilya Minkin, Justin M. Brady, Boris Yanovsky
  • Patent number: 10277610
    Abstract: Some embodiments of reassembly-free deep packet inspection (DPD on multicore hardware have been presented. In one embodiment, a set of packets of one or more files is received at a networked device from one or more connections. Each packet is scanned using one of a set of processing cores in the networked device without buffering the one or more files in the networked device. Furthermore, the set of processing cores may scan the packets substantially concurrently.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: April 30, 2019
    Assignee: SONICWALL INC.
    Inventors: Aleksandr Dubrovsky, John E. Gmuender, Huy Minh Nguyen, Ilya Minkin, Justin M. Brady, Boris Yanovsky
  • Publication number: 20180181453
    Abstract: A method for packet processing on a multi-core processor. According to one embodiment of the invention, a first set of one or more processing cores are configured to include the capability to process packets belonging to a first set of one or more packet types, and a second set of one or more processing cores are configured to include the capability to process packets belonging to a second set of one or more packet types, where the second set of packet types is a subset of the first set of packet types. Packets belonging to the first set of packet types are processed at a processing core of either the first or second set of processing cores. Packets belonging to the second set of packet types are processed at a processing core of the first set of processing cores.
    Type: Application
    Filed: February 20, 2018
    Publication date: June 28, 2018
    Inventors: John E. Gmuender, Iosif Harutyunov, Manish Mathur, Ilya Minkin, Huy Minh Nguyen
  • Patent number: 9898356
    Abstract: A method for packet processing on a multi-core processor. According to one embodiment of the invention, a first set of one or more processing cores are configured to include the capability to process packets belonging to a first set of one or more packet types, and a second set of one or more processing cores are configured to include the capability to process packets belonging to a second set of one or more packet types, where the second set of packet types is a subset of the first set of packet types. Packets belonging to the first set of packet types are processed at a processing core of either the first or second set of processing cores. Packets belonging to the second set of packet types are processed at a processing core of the first set of processing cores.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: February 20, 2018
    Assignee: SONICWALL INC.
    Inventors: John E. Gmuender, Iosif Harutyunov, Manish Mathur, Ilya Minkin, Huy Minh Nguyen
  • Publication number: 20170116057
    Abstract: A method for packet processing on a multi-core processor. According to one embodiment of the invention, a first set of one or more processing cores are configured to include the capability to process packets belonging to a first set of one or more packet types, and a second set of one or more processing cores are configured to include the capability to process packets belonging to a second set of one or more packet types, where the second set of packet types is a subset of the first set of packet types. Packets belonging to the first set of packet types are processed at a processing core of either the first or second set of processing cores. Packets belonging to the second set of packet types are processed at a processing core of the first set of processing cores.
    Type: Application
    Filed: January 3, 2017
    Publication date: April 27, 2017
    Inventors: John E. Gmuender, Iosif Harutyunov, Manish Mathur, Ilya Minkin, Huy Minh Nguyen
  • Patent number: 9535773
    Abstract: A method for packet processing on a multi-core processor. According to one embodiment of the invention, a first set of one or more processing cores are configured to include the capability to process packets belonging to a first set of one or more packet types, and a second set of one or more processing cores are configured to include the capability to process packets belonging to a second set of one or more packet types, where the second set of packet types is a subset of the first set of packet types. Packets belonging to the first set of packet types are processed at a processing core of either the first or second set of processing cores. Packets belonging to the second set of packet types are processed at a processing core of the first set of processing cores.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: January 3, 2017
    Assignee: DELL SOFTWARE INC.
    Inventors: John E. Gmuender, Iosif Harutyunov, Manish Mathur, Ilya Minkin, Huy Minh Nguyen
  • Publication number: 20160026516
    Abstract: A method for packet processing on a multi-core processor. According to one embodiment of the invention, a first set of one or more processing cores are configured to include the capability to process packets belonging to a first set of one or more packet types, and a second set of one or more processing cores are configured to include the capability to process packets belonging to a second set of one or more packet types, where the second set of packet types is a subset of the first set of packet types. Packets belonging to the first set of packet types are processed at a processing core of either the first or second set of processing cores. Packets belonging to the second set of packet types are processed at a processing core of the first set of processing cores.
    Type: Application
    Filed: August 4, 2015
    Publication date: January 28, 2016
    Inventors: John E. Gmuender, Iosif Harutyunov, Manish Marthur, Ilya Minkin, Huy Minh Nguyen
  • Publication number: 20150372983
    Abstract: A method and apparatus for resource locator identifier rewrite have been presented. A security device receives from a resource host over a non-secure hypertext transfer protocol (HTTP) session a response to a request received from a client over a secure HTTP session. The response includes a uniform resource locator (URL) that is supposed to be for a resource host, but the URL does not designate a secure resource access protocol and the resource host requires the secure resource access protocol. The URL is located in the response and modified to designate the secure resource access protocol. After modification, the response is transmitted via the secure resource access protocol session to the client.
    Type: Application
    Filed: July 28, 2015
    Publication date: December 24, 2015
    Inventors: John E. Gmuender, Huy Minh Nguyen, Joseph H. Levy, Michael B. Massing, Zhong Chen, David M. Telehowski
  • Patent number: 9098330
    Abstract: A method for packet processing on a multi-core processor. According to one embodiment of the invention, a first set of one or more processing cores are configured to include the capability to process packets belonging to a first set of one or more packet types, and a second set of one or more processing cores are configured to include the capability to process packets belonging to a second set of one or more packet types, where the second set of packet types is a subset of the first set of packet types. Packets belonging to the first set of packet types are processed at a processing core of either the first or second set of processing cores. Packets belonging to the second set of packet types are processed at a processing core of the first set of processing cores.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: August 4, 2015
    Assignee: Dell Software Inc.
    Inventors: John E. Gmuender, Iosif Harutyunov, Manish Marthur, Ilya Minkin, Huy Minh Nguyen
  • Patent number: 9094365
    Abstract: A method and apparatus for resource locator identifier rewrite have been presented. A security device receives from a resource host over a non-secure hypertext transfer protocol (HTTP) session a response to a request received from a client over a secure HTTP session. The response includes a uniform resource locator (URL) that is supposed to be for a resource host, but the URL does not designate a secure resource access protocol and the resource host requires the secure resource access protocol. The URL is located in the response and modified to designate the secure resource access protocol. After modification, the response is transmitted via the secure resource access protocol session to the client.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: July 28, 2015
    Assignee: Dell Software Inc.
    Inventors: John E. Gmuender, Huy Minh Nguyen, Joseph H. Levy, Michael B. Massing, Zhong Chen, David M. Telehowski
  • Publication number: 20140359764
    Abstract: Some embodiments of reassembly-free deep packet inspection (DPD on multicore hardware have been presented. In one embodiment, a set of packets of one or more files is received at a networked device from one or more connections. Each packet is scanned using one of a set of processing cores in the networked device without buffering the one or more files in the networked device. Furthermore, the set of processing cores may scan the packets substantially concurrently.
    Type: Application
    Filed: August 11, 2014
    Publication date: December 4, 2014
    Inventors: Aleksandr Dubrovsky, John E. Gmuender, Huy Minh Nguyen, Ilya Minkin, Justin M. Brady, Boris Yanovsky
  • Patent number: 8813221
    Abstract: Some embodiments of reassembly-free deep packet inspection (DPI) on multi-core hardware have been presented. In one embodiment, a set of packets of one or more files is received at a networked device from one or more connections. Each packet is scanned using one of a set of processing cores in the networked device without buffering the one or more files in the networked device. Furthermore, the set of processing cores may scan the packets substantially concurrently.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: August 19, 2014
    Assignee: SonicWALL, Inc.
    Inventors: Aleksandr Dubrovsky, John E. Gmuender, Huy Minh Nguyen, Ilya Minkin, Justin M. Brady, Boris Yanovsky
  • Publication number: 20140068622
    Abstract: A method for packet processing on a multi-core processor. According to one embodiment of the invention, a first set of one or more processing cores are configured to include the capability to process packets belonging to a first set of one or more packet types, and a second set of one or more processing cores are configured to include the capability to process packets belonging to a second set of one or more packet types, where the second set of packet types is a subset of the first set of packet types. Packets belonging to the first set of packet types are processed at a processing core of either the first or second set of processing cores. Packets belonging to the second set of packet types are processed at a processing core of the first set of processing cores.
    Type: Application
    Filed: November 13, 2013
    Publication date: March 6, 2014
    Applicant: SonicWALL, Inc.
    Inventors: John E. Gmuender, Iosif Harutyunov, Manish Marthur, Ilya Minkin, Huy Minh Nguyen