Patents by Inventor Huy Ngo
Huy Ngo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230289309Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1x mode or 2x mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.Type: ApplicationFiled: April 24, 2023Publication date: September 14, 2023Inventors: Huy Ngo, Keith Duwel, David W. Mendel
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Patent number: 11669479Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.Type: GrantFiled: April 1, 2022Date of Patent: June 6, 2023Assignee: Altera CorporationInventors: Huy Ngo, Keith Duwel, David W. Mendel
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Patent number: 11583671Abstract: At least some embodiments of the disclosure may advantageously limit bleeding and the occurrence of blood leaks after heart pump implantation. In some embodiments, a base may be provided that includes a flexible layer mechanically coupled with a conduit. The flexible layer may be coupled with the proximal end of the conduit. The conduit may be configured to receive a cannula of the heart pump therethrough. The outer surface of the conduit may be configured to engage a surface of the heart formed after coring the heart. The conduit may be metal and may have a flared and/or beveled distal end. The conduit may be a flexible material. A distal flexible layer may be provided at a distal end of the conduit that is configured to engage with an inner surface of the heart.Type: GrantFiled: January 4, 2021Date of Patent: February 21, 2023Assignee: TC1 LLCInventors: John Duc Nguyen, Huy Ngo, Carine Hoarau, Fabian Franco
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Publication number: 20220222193Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.Type: ApplicationFiled: April 1, 2022Publication date: July 14, 2022Inventors: Huy Ngo, Keith Duwel, David W. Mendel
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Publication number: 20220190843Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.Type: ApplicationFiled: July 26, 2021Publication date: June 16, 2022Inventors: David W. Mendel, Jeffrey Erik Schulz, Keith Duwel, Huy Ngo, Jakob Raymond Jones
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Patent number: 11316961Abstract: An electronic device includes a transparent member arranged on at least one of a front surface or a rear surface of the electronic device and including a first region facing a display module, a housing surrounding the transparent member, including a sidewall extending in a circumferential direction of the electronic device, and forming an exterior of the electronic device, and protruding portions protruding toward the transparent member from the sidewall and extending in the circumferential direction of the electronic device, wherein a distance between the protruding portions facing each other with the transparent member therebetween is less than a width of the transparent member arranged between the protruding portions.Type: GrantFiled: July 20, 2020Date of Patent: April 26, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tri Bui Dac, Hoang Nguyen Van, Truong Dao Xuan, Chon Le Xuan, Huy Ngo Van, Quynh Nguyen Dinh
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Patent number: 11294842Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.Type: GrantFiled: December 22, 2020Date of Patent: April 5, 2022Assignee: Altera CorporationInventors: Huy Ngo, Keith Duwel, David W. Mendel
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Patent number: 11135074Abstract: A medical device includes a polymer scaffold crimped to a catheter having an expansion balloon. The scaffold has a structure that produces a low late lumen loss when implanted within a peripheral vessel and also exhibits a high axial fatigue life. In a preferred embodiment the scaffold forms ring structures interconnected by links, where a ring has 12 crowns and at most two links connecting adjacent rings.Type: GrantFiled: October 16, 2017Date of Patent: October 5, 2021Assignee: ABBOTT CARDIOVASCULAR SYSTEMS INC.Inventors: Syed Hossainy, Chad J. Abunassar, Michael Huy Ngo, Erik David Eli, Santosh V. Prabhu, Mikael Trollsas, Richard Rapoza
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Patent number: 11075648Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.Type: GrantFiled: September 27, 2019Date of Patent: July 27, 2021Assignee: Intel CorporationInventors: David W. Mendel, Jeffrey Erik Schulz, Keith Duwel, Huy Ngo, Jakob Raymond Jones
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Publication number: 20210121677Abstract: At least some embodiments of the disclosure may advantageously limit bleeding and the occurrence of blood leaks after heart pump implantation. In some embodiments, a base may be provided that includes a flexible layer mechanically coupled with a conduit. The flexible layer may be coupled with the proximal end of the conduit. The conduit may be configured to receive a cannula of the heart pump therethrough. The outer surface of the conduit may be configured to engage a surface of the heart formed after coring the heart. The conduit may be metal and may have a flared and/or beveled distal end. The conduit may be a flexible material. A distal flexible layer may be provided at a distal end of the conduit that is configured to engage with an inner surface of the heart.Type: ApplicationFiled: January 4, 2021Publication date: April 29, 2021Applicant: TC1 LLCInventors: John Duc Nguyen, Huy Ngo, Carine Hoarau, Fabian Franco
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Publication number: 20210109882Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.Type: ApplicationFiled: December 22, 2020Publication date: April 15, 2021Inventors: Huy Ngo, Keith Duwel, David W. Mendel
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Publication number: 20210044685Abstract: An electronic device includes a transparent member arranged on at least one of a front surface or a rear surface of the electronic device and including a first region facing a display module, a housing surrounding the transparent member, including a sidewall extending in a circumferential direction of the electronic device, and forming an exterior of the electronic device, and protruding portions protruding toward the transparent member from the sidewall and extending in the circumferential direction of the electronic device, wherein a distance between the protruding portions facing each other with the transparent member therebetween is less than a width of the transparent member arranged between the protruding portions.Type: ApplicationFiled: July 20, 2020Publication date: February 11, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tri BUI DAC, Hoang Nguyen Van, Truong Dao Xuan, Chon Le Xuan, Huy Ngo Van, Quynh Nguyen Dinh
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Patent number: 10894116Abstract: At least some embodiments of the disclosure may advantageously limit bleeding and the occurrence of blood leaks after heart pump implantation. In some embodiments, a base may be provided that includes a flexible layer mechanically coupled with a conduit. The flexible layer may be coupled with the proximal end of the conduit. The conduit may be configured to receive a cannula of the heart pump therethrough. The outer surface of the conduit may be configured to engage a surface of the heart formed after coring the heart. The conduit may be metal and may have a flared and/or beveled distal end. The conduit may be a flexible material. A distal flexible layer may be provided at a distal end of the conduit that is configured to engage with an inner surface of the heart.Type: GrantFiled: August 21, 2017Date of Patent: January 19, 2021Assignee: TC1 LLCInventors: John Duc Nguyen, Huy Ngo, Carine Hoarau, Fabian Franco
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Patent number: 10884964Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.Type: GrantFiled: June 10, 2019Date of Patent: January 5, 2021Assignee: Altera CorporationInventors: Huy Ngo, Keith Duwel, David W. Mendel
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Publication number: 20200065282Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.Type: ApplicationFiled: June 10, 2019Publication date: February 27, 2020Inventors: Huy Ngo, Keith Duwel, David W. Mendel
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Publication number: 20200028521Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.Type: ApplicationFiled: September 27, 2019Publication date: January 23, 2020Inventors: David W. Mendel, Jeffrey Erik Schulz, Keith Duwel, Huy Ngo, Jakob Raymond Jones
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Patent number: 10439639Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.Type: GrantFiled: December 28, 2016Date of Patent: October 8, 2019Assignee: INTEL CORPORATIONInventors: David W. Mendel, Jeffrey Erik Schulz, Keith Duwel, Huy Ngo, Jakob Raymond Jones
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Patent number: 10404627Abstract: Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.Type: GrantFiled: August 14, 2017Date of Patent: September 3, 2019Assignee: Altera CorporationInventors: Huy Ngo, Keith Duwel, Vinson Chan, Divya Vijayaraghavan, Curt Wortman
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Patent number: 10394737Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1x mode or 2x mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.Type: GrantFiled: December 18, 2015Date of Patent: August 27, 2019Assignee: Altera CorporationInventors: Huy Ngo, Keith Duwel, David W. Mendel
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Publication number: 20180183463Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.Type: ApplicationFiled: December 28, 2016Publication date: June 28, 2018Inventors: David W. Mendel, Jeffrey Erik Schulz, Keith Duwel, Huy Ngo, Jakob Raymond Jones