Patents by Inventor Hwansoo Han

Hwansoo Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230214196
    Abstract: The disclosure is related to a dynamic rebinding method for a computing unit in heterogeneous computing clouds. The method includes A dynamic rebinding method for a computing unit in heterogeneous computing clouds, receiving a first computing request from a terminal, generating a static FAT binary by compiling a device binary codes for each of all types of heterogeneous accelerators based on the first computing request, generating and storing global data including device binary codes and libraries of all types of the heterogeneous accelerators, generating a structure capable of dynamic binding by separating device binary codes for each type of the heterogeneous accelerators from the static fat binary, allocating a first compute node and first heterogeneous accelerators based on the first computing request.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 6, 2023
    Applicant: Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
    Inventors: Hwansoo HAN, Sungin HONG
  • Patent number: 10437784
    Abstract: A storage system may include at least one storage device and a server. The storage device may store an incoming data, calculate a hash value for the incoming data, and store the hash value as meta data. The server may provide the incoming data to the storage device, read the meta data from the storage device, determine whether the meta data is duplicate in the table, and perform a deduplication process regarding the incoming data based on the determination result.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: October 8, 2019
    Assignee: SK hynix Inc.
    Inventors: Zhenchuan Chai, Indra G. Harijono, Hwansoo Han
  • Patent number: 10073878
    Abstract: Receiving, at a storage array controller, a write instruction that includes a logical address and write data. Using the storage array controller to generate a fingerprint from the write data and sending, from the storage array controller to one or more recipient storage devices, a query that includes the fingerprint, wherein the query asks the recipient storage devices if the fingerprint is stored on any of the recipient storage devices.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventors: Hwansoo Han, Zhenchuan Chai, Tae Il Um
  • Patent number: 9891826
    Abstract: A Discard command is received which includes an address on a specific SSD of a plurality of SSDs configured as a RAID device, wherein the Discard command is associated with data associated with the address. In response to receiving the Discard command, a trim metadata flag is set in an entry associated with the address in a mapping table, wherein a trim metadata flag that is set indicates that a Discard command was received for a corresponding address.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: February 13, 2018
    Assignee: SK Hynix Inc.
    Inventors: Tae Il Um, Hwansoo Han, Mehryar Rahmatian
  • Publication number: 20160224589
    Abstract: A storage system may include at least one storage device and a server. The storage device may store an incoming data, calculate a hash value for the incoming data, and store the hash value as meta data. The server may provide the incoming data to the storage device, read the meta data from the storage device, determine whether the meta data is duplicate in the table, and perform a deduplication process regarding the incoming data based on the determination result.
    Type: Application
    Filed: January 29, 2016
    Publication date: August 4, 2016
    Inventors: Zhenchuan CHAI, Indra G. HARIJONO, Hwansoo HAN
  • Patent number: 9195579
    Abstract: A memory system includes a central processing unit (CPU), a nonvolatile memory electrically coupled to the CPU and a main memory, which is configured to swap an incoming code page for a target code page therein, in response to a first command issued by the CPU. The main memory can be configured to swap the target code page in the main memory to the nonvolatile memory in the event a page capacity of the main memory is at a threshold capacity. The CPU may also be configured to perform a frequency of use analysis on the target code page to determine whether the target code page is to be swapped to the nonvolatile memory or discarded. The incoming code page may be provided by a disk drive storage device and the main memory may be a volatile memory.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 24, 2015
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation, Sungkyunkwan University
    Inventors: Oh-Seong Kwon, Hwansoo Han, Sun-Young Lim, Seonggun Kim
  • Publication number: 20130262738
    Abstract: A memory system includes a central processing unit (CPU), a nonvolatile memory electrically coupled to the CPU and a main memory, which is configured to swap an incoming code page for a target code page therein, in response to a first command issued by the CPU. The main memory can be configured to swap the target code page in the main memory to the nonvolatile memory in the event a page capacity of the main memory is at a threshold capacity. The CPU may also be configured to perform a frequency of use analysis on the target code page to determine whether the target code page is to be swapped to the nonvolatile memory or discarded. The incoming code page may be provided by a disk drive storage device and the main memory may be a volatile memory.
    Type: Application
    Filed: January 30, 2013
    Publication date: October 3, 2013
    Applicants: Research & Business Foundation, Sungkyunkwan University, Samsung Electronics Co., Ltd.
    Inventors: Oh-Seong Kwon, Hwansoo Han, Sun-Young Lim, Seonggun Kim