Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.

Abstract: A delay locked loop circuit including: a clock signal input buffer to buffer an input clock signal and generate a reference clock signal; a delay unit to delay the reference clock signal in response to a coarse and fine delay code and generate an internal clock signal; a clock signal delay replica unit to delay the internal clock signal and generate a feedback clock signal; a coarse delay control unit to receive the reference and feedback clock signals, detect a time period between a transition time point of the reference clock signal and a transition time point of the feedback clock signal occurring before the transition time point of the reference clock signal, and generate a coarse delay code; and a fine delay control unit to compare a phase of the reference clock signal and a phase of the feedback clock signal, and generate a fine delay code.

Abstract: A memory device includes a calibration circuit having a pull-up code generator including a pull-up resistor block and generating a pull-up code, and a pull-down code generator including a replica pull-up resistor block and a pull-down resistor block and generating a pull-down code, and an off chip driver/on die termination circuit providing a termination resistance having a resistance value set by the calibration circuit in a data reception operation and outputting data at an output strength set by the calibration circuit in a data output operation. In a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block.

Abstract: A memory device includes a calibration circuit having a pull-up code generator including a pull-up resistor block and generating a pull-up code, and a pull-down code generator including a replica pull-up resistor block and a pull-down resistor block and generating a pull-down code, and an off chip driver/on die termination circuit providing a termination resistance having a resistance value set by the calibration circuit in a data reception operation and outputting data at an output strength set by the calibration circuit in a data output operation. In a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block.

Abstract: A delay locked loop circuit including: a clock signal input buffer to buffer an input clock signal and generate a reference clock signal; a delay unit to delay the reference clock signal in response to a coarse and fine delay code and generate an internal clock signal; a clock signal delay replica unit to delay the internal clock signal and generate a feedback clock signal; a coarse delay control unit to receive the reference and feedback clock signals, detect a time period between a transition time point of the reference clock signal and a transition time point of the feedback clock signal occurring before the transition time point of the reference clock signal, and generate a coarse delay code; and a fine delay control unit to compare a phase of the reference clock signal and a phase of the feedback clock signal, and generate a fine delay code.

Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.

Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.

Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.