Abstract: A method for forming TGO structures includes providing a substrate containing regions of first, second and third kinds in which devices with respective first, second and third gate oxide layers of different thicknesses are to be formed. The second gate oxide layer is formed over the substrate and then removed from regions of the first kind where the first gate oxide layer is subsequently grown. A first conductive layer is deposited over the substrate. The first conductive layer and second gate oxide layer are subsequently removed from regions of the third kind. The third gate oxide layer followed by deposition of a second conductive layer is formed over the substrate and then removed except from over regions of the third kind.

Abstract: A method for forming TGO structures includes providing a substrate containing regions of first, second and third kinds in which devices with respective first, second and third gate oxide layers of different thicknesses are to be formed. The second gate oxide layer is formed over the substrate and then removed from regions of the first kind where the first gate oxide layer is subsequently grown. A first conductive layer is deposited over the substrate. The first conductive layer and second gate oxide layer are subsequently removed from regions of the third kind. The third gate oxide layer followed by deposition of a second conductive layer is formed over the substrate and then removed except from over regions of the third kind.

Abstract: A process for integrating the fabrication of double diffused drain (DDD) MOSFET devices with the fabrication sub-micron CMOS devices, has been developed. The process features formation of an insulator hard mask shape on an underlying polysilicon gate structure shape in the DDD MOSFET region, while only a polysilicon gate structure shape is formed in the CMOS device region. High energy ion implantation procedures are employed to form the deep source/drain regions of the DDD MOSFET devices with the insulator hard mask shape preventing the high energy implantation procedure from disturbing the underlying channel region. An anneal procedure used activate and drive—in the implanted ions in the deep source/drain region of the DDD MOSFET device is followed by formation of the shallower source/drain regions of the sub-micron CMOS devices.