Abstract: Provided is a method of operating a terminal. The method includes determining a profile item applicable to the profile view for the account based on an input received by the terminal and a coordinate indicating a position where the profile item is provided on the profile view. The method includes displaying the profile item on a screen of the terminal based on the determined profile item and the determined coordinate. The method includes receiving an input related to the profile item, and displaying a visual effect corresponding to the input on the screen.

Abstract: The present invention relates to a pharmaceutical composition with enhanced stability, containing pemetrexed or a salt thereof, and a preparation method therefor. The present invention provides an injection preparation in liquid form containing pemetrexed, capable of ensuring sufficient stability during circulation and storage by selection of an optimum material and setting of an optimum concentration range in order to secure the stability of pemetrexed. The present invention can provide a pemetrexed preparation which is readily commercially prepared, can prevent microbial contamination occurring during lyophilization or reconstitution, and has enhanced convenience of administration and stability.

Abstract: The present invention relates to a pharmaceutical composition with enhanced stability, containing pemetrexed or a salt thereof, and a preparation method therefor. The present invention provides an injection preparation in liquid form containing pemetrexed, capable of ensuring sufficient stability during circulation and storage by selection of an optimum material and setting of an optimum concentration range in order to secure the stability of pemetrexed. The present invention can provide a pemetrexed preparation which is readily commercially prepared, can prevent microbial contamination occurring during lyophilization or reconstitution, and has enhanced convenience of administration and stability.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a first type semiconductor layer doped with an N type ion, a second type semiconductor layer formed over the first type semiconductor layer, and a silicon germanium (SiGe) layer doped with a P type ion formed over the second type semiconductor layer.

Abstract: The manufacturing of a phase change memory device that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact. The formed bottom electrode contact exposes a switching device on a semiconductor substrate which the switching device is formed in, forming an insulating layer on a resultant structure of the semiconductor substrate including the bottom electrode contact by using an insulating compound having materials with different atomic sizes, and forming an insulating spacer within the bottom electrode contact hole by selectively etching the insulating layer.

Abstract: Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole.

Abstract: Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole.

Abstract: A phase change memory device is provided that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact.

Abstract: A phase change memory device is provided that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact.

Abstract: A phase change memory device is presented that has a lower electrode contact that has a gradient resistance profile ranging from a lower resistive lower end to a higher resistive upper end. The phase change memory device includes a semiconductor substrate, a lower electrode contact, and a phase change pattern. The semiconductor substrate has a switching device. The lower electrode contact is formed on the switching device and has a specific resistance which gradually increases from a lower part to an upper part of the lower electrode contact. The phase change pattern layer is formed on the lower electrode contact.

Abstract: Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer pattern by etching the semiconductor layer pattern; removing the etch stop layer pattern exposed in the recess trench; and forming a gate that fills the recess trench.

Abstract: A method of fabricating a semiconductor device having a gate spacer layer with a uniform thickness wherein a gate electrode layer pattern is formed on a substrate and ion implantation processes of respectively different doses are formed on side walls of the gate electrode layer patterns in respective first and second regions of the substrate. A first gate spacer layer is formed on the gate electrode layer pattern where the ion implantation process is performed. A second gate spacer layer is formed on the first gate spacer layer.

Abstract: A method of manufacturing a memory device and a phase-change memory device is presented. The method of manufacturing the memory device includes performing Ge ion implantation on a top surface of a first layer. The method also includes performing a fast heat treatment on the ion-implanted first layer. The method also includes forming a second layer on a top of the fast heat-treated first layer.

Abstract: A phase change memory device is presented that has a lower electrode contact that has a gradient resistance profile ranging from a lower resistive lower end to a higher resistive upper end. The phase change memory device includes a semiconductor substrate, a lower electrode contact, and a phase change pattern. The semiconductor substrate has a switching device. The lower electrode contact is formed on the switching device and has a specific resistance which gradually increases from a lower part to an upper part of the lower electrode contact. The phase change pattern layer is formed on the lower electrode contact.

Abstract: A method for forming a capacitor in a semiconductor device is disclosed. The method includes forming a storage node electrode on a semiconductor substrate, forming a dielectric layer having a high dielectric constant on the storage node electrode, depositing a plate electrode on the dielectric layer, thereby forming by-product impurities, and removing by-product impurities remaining on the plate electrode by introducing a hydrogen (H) atom-containing gas onto the semiconductor substrate while depositing a capping layer on the plate electrode.

Abstract: Disclosed herein is a method for fabricating a semiconductor memory device that can prevent oxidation of bit lines when forming an interlayer dielectric for isolating the bit lines. The bit line is formed on a semiconductor substrate where an underlying structure is formed. A silicon on dielectric (SOD) layer is formed on the resulting structure where the bit line is formed. A heat treatment can be performed on the SOD layer with a partial pressure ratio of water vapor (H2O) to hydrogen (H2) in a range of about 1×10?11 to about 1.55 at a temperature in a range of about 600° C. to about 1,100° C.

Abstract: Disclosed herein is a method for fabricating a semiconductor memory device that can prevent oxidation of bit lines when forming an interlayer dielectric for isolating the bit lines. The bit line is formed on a semiconductor substrate where an underlying structure is formed. A silicon on dielectric (SOD) layer is formed on the resulting structure where the bit line is formed. A heat treatment can be performed on the SOD layer with a partial pressure ratio of water vapor (H2O) to hydrogen (H2) in a range of about 1×10?11 to about 1.55 at a temperature in a range of about 600° C. to about 1,100° C.

Abstract: A method of fabricating a semiconductor device having a gate spacer layer with a uniform thickness wherein a gate electrode layer pattern is formed on a substrate and ion implantation processes of respectively different doses are formed on side walls of the gate electrode layer patterns in respective first and second regions of the substrate. A first gate spacer layer is formed on the gate electrode layer pattern where the ion implantation process is performed. A second gate spacer layer is formed on the first gate spacer layer.

Abstract: Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer pattern by etching the semiconductor layer pattern; removing the etch stop layer pattern exposed in the recess trench; and forming a gate that fills the recess trench.

Abstract: A method of forming an isolation layer in a semiconductor device using rapid vapor deposition to fill in a trench of the semiconductor device comprises forming a hydrophilic layer on the trench and forming a hydrophobic layer on a region other than the trench, and selectively forming a buried insulating layer in the trench using a catalytic reaction of the hydrophilic layer.