Abstract: The present disclosure relates to an advanced in vivo reprogramming system and a cell conversion method using same. The reprogramming system of the present disclosure comprises a start cell marker promoter, a pluripotency-maintaining gene protein, an amino acid isolation peptide, Cre recombinase, a target cell marker promoter, LoxP, and a gene encoding a fluorescent protein, does not require cell fixation in order to confirm cell conversion, enables real-time monitoring in a living cell state, and may be used both in vitro and in vivo. Therefore, the present disclosure is expected to be widely used in the biological and medical fields.

Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.

Abstract: Semiconductor device as provided may include a substrate with an NMOS region and a PMOS region, and a first transistor in the NMOS region that includes a first gate stack and a first source/drain region on at least one side of the first gate stack. The semiconductor device may further include a second transistor in the PMOS region that includes a second gate stack and a second source/drain region on at least one side of the second gate stack. The first gate stack may include a first insulating film, a first gate electrode layer of first thickness, additional gate electrode layers, a and a first silicon layer, which may be sequentially laminated. The second gate stack may include a second insulating film, a fourth gate electrode layer of second thickness greater than the first thickness, additional gate electrode layers, and a second silicon layer, which may be sequentially laminated.

Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.

Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

Abstract: Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

Abstract: Provided are a semiconductor device in which a multi-threshold voltage is embodied by controlling a work function, and a method of manufacturing the same. The device includes a semiconductor substrate including a first region and a second region, a first active region formed in an upper portion of the first region of the semiconductor substrate, a second active region formed in an upper portion of the second region of the semiconductor substrate, a first gate structure formed on the semiconductor substrate across the first active region, the first gate structure including an interfacial layer, a high-k dielectric layer, a capping metal layer, and a work function metal layer that are stacked sequentially, and a second gate structure formed on the semiconductor substrate across the second active region, the second gate structure including the interfacial layer, the high-k dielectric layer, the capping metal layer, a dielectric layer, and the work function metal layer that are stacked sequentially.

Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

Abstract: Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. The semiconductor device a gate dielectric pattern on a substrate and a gate electrode on the gate dielectric pattern opposite the substrate. The gate electrode includes a first conductive pattern disposed on the gate dielectric pattern and including aluminum, and a second conductive pattern disposed between the first conductive pattern and the gate dielectric pattern. The second conductive pattern has an aluminum concentration that is higher than an aluminum concentration of the first conductive pattern. The second conductive pattern may be thicker than the first conductive pattern.

Abstract: Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities. In some embodiments, the MOSFETs are FinFETs, and the doping may be a conformal doping.

Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

Abstract: Methods of manufacturing a MOS transistor are provided. The methods may include forming first and second trenches. The methods may further include forming first metal patterns within portions of the first and second trenches. The methods may additionally include removing the first metal patterns from the second trench while at least portions of the first metal patterns remain within the first trench. The methods may also include forming a second metal layer within the first and second trenches, the second metal layer formed on the first metal patterns within the first trench.

Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. The semiconductor device a gate dielectric pattern on a substrate and a gate electrode on the gate dielectric pattern opposite the substrate. The gate electrode includes a first conductive pattern disposed on the gate dielectric pattern and including aluminum, and a second conductive pattern disposed between the first conductive pattern and the gate dielectric pattern. The second conductive pattern has an aluminum concentration that is higher than an aluminum concentration of the first conductive pattern. The second conductive pattern may be thicker than the first conductive pattern.

Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.

Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities.

Abstract: A semiconductor device includes an insulating film on a substrate and including a trench, a gate insulating film in the trench, a DIT (Density of Interface Trap) improvement film on the gate insulating film to improve a DIT of the substrate, and a first conductivity type work function adjustment film on the DIT improvement film. Related methods of forming semiconductor devices are also disclosed.

Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.