Abstract: The present technology relates to a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells corresponding to a plurality of word line groups, a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation, a voltage generation circuit configured to apply an operation voltage increasing from a first operation voltage to a second operation voltage to the plurality of word line groups during the erase operation, and a control logic configured to control the source line driver and the voltage generation circuit to perform a suspend operation of stopping the erase operation.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include peripheral circuits configured to perform a verify operation on selected memory cells by applying a verify voltage to a word line, and perform a compensation program operation on the selected memory cells by applying a compensation program voltage to the word line; and a control logic configured to control the peripheral circuits such that the compensation program operation is performed by applying the compensation program voltage to the selected memory cells to be programmed to a selected threshold voltage distribution among the threshold voltage distributions other than a highest threshold voltage distribution, wherein the compensation program voltage has a positive voltage lower than the main program voltage most recently applied to the word line.

Abstract: A controller, for use in memory system, includes: a processor configured to control a read operation for a target memory area of a memory device in response to a read command received from a host; and an error correction circuit configured to perform an error correction operation on read data corresponding to the read operation, wherein the processor selects an optimum read voltage set among a plurality of read voltage sets in a read retry table, based on an erase write cycling (EW) number of the target memory area and a fail bit number of the read data.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include peripheral circuits configured to perform a verify operation on selected memory cells by applying a verify voltage to a word line, and perform a compensation program operation on the selected memory cells by applying a compensation program voltage to the word line; and a control logic configured to control the peripheral circuits such that the compensation program operation is performed by applying the compensation program voltage to the selected memory cells to be programmed to a selected threshold voltage distribution among the threshold voltage distributions other than a highest threshold voltage distribution, wherein the compensation program voltage has a positive voltage lower than the main program voltage most recently applied to the word line.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a plurality of pages each including a plurality of memory cells, peripheral circuits configured to perform a program operation of a selected page among the plurality of pages and a control logic configured to control the peripheral circuits such that a main program operation is performed on the selected page and, when the main program operation is completed, a compensation program operation is performed on memory cells having lower threshold voltage retention characteristics compared to remaining memory cells, among the memory cells included in the selected page.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a plurality of pages each including a plurality of memory cells, peripheral circuits configured to perform a program operation of a selected page among the plurality of pages and a control logic configured to control the peripheral circuits such that a main program operation is performed on the selected page and, when the main program operation is completed, a compensation program operation is performed on memory cells having lower threshold voltage retention characteristics compared to remaining memory cells, among the memory cells included in the selected page.

Abstract: A semiconductor device includes a memory block including memory cells coupled to word lines, and an operation circuit configured to perform a program loop on memory cells coupled a selected word line, wherein the operation circuit is configured to change a program permission voltage applied to a bit line of a program target memory cell when a number of times the program loop is performed exceeds a reference number.

Abstract: A semiconductor device includes memory cells electrically coupled to word lines. In addition, the semiconductor device includes an operation circuit performing a program loop on memory cells electrically coupled to a selected word line. Further, the operation circuit increases a program permission voltage applied to a bit line of a program target memory cell when a number of times in which the program loop is performed exceeds a reference number.

Abstract: A semiconductor device includes memory cells electrically coupled to word lines. In addition, the semiconductor device includes an operation circuit performing a program loop on memory cells electrically coupled to a selected word line. Further, the operation circuit increases a program permission voltage applied to a bit line of a program target memory cell when a number of times in which the program loop is performed exceeds a reference number.