Abstract: The present invention relates to a cosmetic composition including fibroblast growth factor 17 (FGF 17). When using the cosmetic composition for skin regeneration including fibroblast growth factor 17 (FGF 17) of the present invention, the proliferation ability of fibroblasts in the skin is promoted such that there is an effect of skin regeneration, synthesis of collagen and elastin is promoted such that it is possible to ameliorate skin wrinkles and improve skin elasticity, and the proliferation ability of aged skin fibroblasts is restored as much as that of unaged skin fibroblasts such that skin aging can be prevented, and therefore, the cosmetic compound can be widely used in the cosmetic field and the pharmaceutical industry.

Abstract: A hybrid catalyst composition containing a heterogeneous transition metal compound, a catalyst for olefin polymerization containing the heterogeneous transition metal compound, and a method for preparing an olefin-based polymer in which generation of a gel is suppressed using the catalyst are disclosed. The method for preparing an olefin-based polymer can provide an olefin-based polymer in which non-uniformity of the olefin-based polymer, and in particular, generation of a gel is suppressed.

Abstract: An optical filter includes a near-infrared absorbing layer including a first material, the first material being configured to absorb light in a first wavelength spectrum belonging to a near-infrared wavelength spectrum. The optical filter includes a compensation layer adjacent to the near-infrared absorbing layer, the compensation layer including a second material different from the first material. The optical filter includes a metamaterial structure spaced apart from the near-infrared absorbing layer via the compensation layer, the metamaterial structure being configured to absorb or reflect light in a second wavelength spectrum at least partially overlapped with the first wavelength spectrum.

Abstract: A semiconductor device includes a sequence data generator, which is configured to generate sequence data on a plurality of data lines, and a symbol changer. The symbol changer is configured to generate a training pattern from the sequence data by replacing, for each of the plurality of data lines, each occurrence of a bitstream within the sequence data that has a predetermined symbol with an alternative symbol. The sequence data generator may include a sequence generator, which is configured to generate a pseudo random binary sequence (PRBS), based on a seed value for each clock cycle.

Abstract: Provided is a memory system including: a memory device; and a memory controller configured to transmit a command and address (CA) signal and a data clock (WCK) signal to the memory device, and transmitting a data (DQ) signal to the memory device or receive the DQ signal from the memory device. The memory device may include a clock distribution network configured to generate a first division clock signal for sampling the CA signal and a second division clock signal for sampling the DQ signal from the data clock signal, a CA sampler configured to sample the CA signal based on the first division clock signal, and a CA parity check circuitry configured to output a parity error signal in response to a parity error occurring for the CA signal, and the memory controller may include processing circuitry configured to enter CA training in response to receiving the parity error signal.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal, a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

Abstract: A combination structure includes an in-plane pattern of unit cells, wherein the each unit cell includes nanostructures each having a dimension that is smaller than a near-infrared wavelength and a light-absorbing layer adjacent to the nanostructures and including a near-infrared absorbing material configured to absorb light in at least a portion of a near-infrared wavelength spectrum. The nanostructures are define a nanostructure array in the unit cells, and a wavelength width at 50% transmittance of a transmission spectrum in the near-infrared wavelength spectrum of the combination structure is wider than a wavelength width at 50% transmittance of a transmission spectrum in the near-infrared wavelength spectrum of the nanostructure array.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

Abstract: An optical filter includes a light absorbing layer and a conductive nanodisk. The light absorbing layer includes a near-infrared absorbing material configured to absorb light of a first wavelength spectrum within a near-infrared wavelength spectrum. The conductive nanodisk is configured to absorb or reflect light of a second wavelength spectrum within the first wavelength spectrum. An image sensor includes the optical filter, a camera module includes the optical filter, and an electronic device includes the optical filter.

Abstract: A combination structure includes an in-plane pattern of unit cells, wherein the each unit cell includes nanostructures each having a dimension that is smaller than a near-infrared wavelength and a light-absorbing layer adjacent to the nanostructures and including a near-infrared absorbing material configured to absorb light in at least a portion of a near-infrared wavelength spectrum. The nanostructures are define a nanostructure array in the unit cells, and a wavelength width at 50% transmittance of a transmission spectrum in the near-infrared wavelength spectrum of the combination structure is wider than a wavelength width at 50% transmittance of a transmission spectrum in the near-infrared wavelength spectrum of the nanostructure array.

Abstract: A combination structure includes a hybrid nanostructure array and a light-absorbing layer adjacent to the hybrid nanostructure array. The hybrid nanostructure array includes a plurality of hybrid nanostructures, each hybrid nanostructure includes a stack of a first nanostructure and a second nanostructure. The first nanostructure includes a first material. The second nanostructure includes a second material. The second material has a refractive index that is higher than a refractive index of the first material. The light-absorbing layer includes a near-infrared absorbing material configured to absorb light of at least a portion of a near-infrared wavelength spectrum.

Abstract: Disclosed are a near-infrared absorbing composition, an optical structure, and a camera module and an electronic device including the same. The near-infrared absorbing composition includes a copper complex represented by Chemical Formula 1. Definitions of Chemical Formula 1 are the same as described in the detailed description.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: A multiplexer selects one of a first to a fourth data signal in response to a first to a fourth pulse. The first to fourth pulses respectively correspond to the first to fourth data signals and sequentially toggle. The multiplexer includes: (1) a NAND gate that receives the first data signal, a fourth complementary data signal that is a complementary signal of the fourth data signal, and the first pulse and outputs a first gate signal and (2) a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse that is complementary to the first pulse and outputs a second gate signal. The first data signal corresponds to a rising edge of the first pulse, and the fourth complementary data signal corresponds to a rising edge of the fourth pulse.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: A memory device and an operating method of the memory device are provided. The operating method comprises receiving an activation-refresh command from a memory controller, decoding a target address and an internal command from the activation-refresh command, and performing an activation operation based on the internal command for the target address and performing a refresh operation on at least one block to which the target address does not belong.

Abstract: A leukemia diagnostic kit may be an RT-PCR kit enabling expression levels of prohibitin-1 and prohibitin-2 to be checked in a leukemia patient specimen, wherein the accuracy and the reproducibility of leukemia diagnosis of the kit are higher than those of a conventional RT-PCR kit, thereby being useful as a kit for diagnosing leukemia, examining residual lesions and evaluating therapeutic effects.