Patents by Inventor Hyeog Kwon
Hyeog Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080006925Abstract: An integrated circuit package-in-package system is provided forming a first integrated circuit package having a first interface, stacking a second integrated circuit package having a second interface above the first integrated circuit package, fitting the first interface and the second interface, and attaching a third integrated circuit package on the second integrated circuit package.Type: ApplicationFiled: September 20, 2007Publication date: January 10, 2008Inventors: Choong Yim, Hyeog Kwon, Jong-Woo Ha
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Publication number: 20070158833Abstract: An integrated circuit package system is provided including providing a wafer with bond pads formed on the wafer. A solder bump is deposited on one or more bond pads. The bond pads and the solder bump are embedded within a mold compound formed on the wafer. A groove is formed in the mold compound to expose a portion of the solder bump. The wafer is singulated into individual die structures at the groove.Type: ApplicationFiled: January 4, 2006Publication date: July 12, 2007Inventors: Soo-San Park, Hyeog Kwon, Sang-Ho Lee, Jong-Woo Ha
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Publication number: 20070085184Abstract: A substrate is provided. A first die is placed on the substrate. A film spacer is attached to the first die and a second die is placed on the film spacer. The substrate, the first die, the film spacer, and the second die are encapsulated in an encapsulant.Type: ApplicationFiled: October 13, 2005Publication date: April 19, 2007Applicant: STATS CHIPPAC LTD.Inventors: Hyeog Kwon, Hee Lee
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Publication number: 20070013060Abstract: Stacked semiconductor assemblies in which a device such as a die, or a package, or a heat spreader is stacked over a first wire-bonded die. An adhesive/spacer structure is situated between the first wire-bonded die and the device stacked over it, and the device has an electrically non-conductive surface facing the first wire-bonded die. That is, the first die is mounted active side upward on a first substrate and is electrically interconnected to the substrate by wire bonding; an adhesive/spacer structure is formed upon the active side of the first die; and a device such as a die or a package or a heat spreader, having an electrically nonconductive side, is mounted upon the adhesive/spacer structure with the electrically nonconductive side facing the first wire bonded die. The side of the device facing the first wire bonded die may be made electrically nonconductive by having an electrically insulating layer, such as a dielectric film adhesive. Also, methods for making the assemblies are disclosed.Type: ApplicationFiled: September 21, 2006Publication date: January 18, 2007Applicant: ChipPAC, IncInventors: Hyeog Kwon, Marcos Karnezos
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Publication number: 20070015314Abstract: An adhesive/spacer structure (52, 52A, 60) is used to adhere first and second die (14, 18) to one another at a chosen separation in a multiple-die semiconductor chip package (56). The first and second die define a die bonding region (38) therebetween. The adhesive/spacer structure may comprise a plurality of spaced-apart adhesive/spacer islands (52, 52A) securing the first and second die to one another at a chosen separation (53). The adhesive/spacer structure may also secure the first and second die to one another to occupy about 1-50% of the die bonding region.Type: ApplicationFiled: September 11, 2006Publication date: January 18, 2007Applicant: ChipPAC, IncInventors: Sang Ho Lee, Jong Ju, Hyeog Kwon
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Publication number: 20060180911Abstract: A stacked integrated circuit and package system including attaching a first top integrated circuit over an upper surface of a top substrate, attaching a second top integrated circuit over a lower surface of the top substrate, forming top electrical connectors on the lower surface of the top substrate, and connecting a bottom package to the top electrical connectors.Type: ApplicationFiled: October 21, 2005Publication date: August 17, 2006Applicant: STATS ChipPAC Ltd.Inventors: Tae Jeong, Hyeog Kwon, Youngcheol Kim
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Publication number: 20050269676Abstract: Adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device such as a die, or a package, or a heat spreader, in a stacked semiconductor assembly, include a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. Either or both of the first and second devices can be a die; or, either or both of the devices can be a package. A package includes a die mounted onto and electrically interconnected to, a substrate, and where one package (an “upper” package) is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate (that is, the upper package may be inverted), or so that the die attach side of the upper package faces away from the lower die or lower package substrate.Type: ApplicationFiled: May 20, 2005Publication date: December 8, 2005Applicant: ChipPAC, IncInventors: Sang Lee, Jong Ju, Hyeog Kwon, Marcos Karnezos
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Publication number: 20050269692Abstract: Stacked semiconductor assemblies in which a device such as a die, or a package, or a heat spreader is stacked over a first wire-bonded die. An adhesive/spacer structure is situated between the first wire-bonded die and the device stacked over it, and the device has an electrically non-conductive surface facing the first wire-bonded die. That is, the first die is mounted active side upward on a first substrate and is electrically interconnected to the substrate by wire bonding; an adhesive/spacer structure is formed upon the active side of the first die; and a device such as a die or a package or a heat spreader, having an electrically nonconductive side, is mounted upon the adhesive/spacer structure with the electrically nonconductive side facing the first wire bonded die. The side of the device facing the first wire bonded die may be made electrically nonconductive by having an electrically insulating layer, such as a dielectric film adhesive. Also, methods for making the assemblies are disclosed.Type: ApplicationFiled: May 20, 2005Publication date: December 8, 2005Applicant: ChipPAC, IncInventors: Hyeog Kwon, Marcos Karnezos
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Publication number: 20050258527Abstract: An adhesive/spacer structure (52, 52A, 60) is used to adhere first and second die (14, 18) to one another at a chosen separation in a multiple-die semiconductor chip package (56). The first and second die define a die bonding region (38) therebetween. The adhesive/spacer structure may comprise a plurality of spaced-apart adhesive/spacer islands (52, 52A) securing the first and second die to one another at a chosen separation (53). The adhesive/spacer structure may also secure the first and second die to one another to occupy about 1-50% of the die bonding region.Type: ApplicationFiled: October 20, 2004Publication date: November 24, 2005Applicant: ChipPAC, Inc.Inventors: Sang Lee, Jong Ju, Hyeog Kwon
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Publication number: 20050258545Abstract: A multiple-die semiconductor chip package (68) has first and second die (42, 44) which define a first, adhesive region (58) therebetween. Wires (20) extend from bond pads (14) on a first die surface (52). The second die has an insulated second die surface (54) positioned opposite the first die surface. An adhesive/spacer structure (46), comprising spacer elements (50) within an adhesive (48), adheres the first and second die to one another. The package may comprise a set of generally parallel wires which defines a wire span portion (60) of the first region. The adhesive/spacer structure is preferably located at other than the wire span portion of the first region. A method for adhering the first and second die to one another is also disclosed.Type: ApplicationFiled: October 20, 2004Publication date: November 24, 2005Applicant: ChipPAC, Inc.Inventor: Hyeog Kwon
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Publication number: 20050224959Abstract: A semiconductor die, for use in a multiple-die semiconductor chip package, has a wire bonding side and a backside. At least two discrete spacers, and preferably at least four, are secured to the die at chosen spacer positions on at least one of the wire bonding side and the backside. The spacers are configured and positioned to help maintain proper die-to-die spacing between the die and an adjacent die in a multiple-die semiconductor chip package. At least two of the discrete spacers may be secured directly to the wire bonding side. A dielectric layer may be on the backside of the die and at least two of the discrete spacers may be secured to the dielectric layer on the backside of the die.Type: ApplicationFiled: October 15, 2004Publication date: October 13, 2005Applicant: ChipPAC, IncInventors: Hyeog Kwon, Geun Kim
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Publication number: 20050208701Abstract: Individual pieces of film adhesive (42) are placed on a support surface (46). Diced semiconductor chips (24) are individually placed on the individual pieces of the film adhesive thereby securing the diced semiconductor chips to the support surface to create first chip subassemblies (52). The diced semiconductor chip and support surface of each of a plurality of the first chip subassemblies are electrically connected, such as by wires (54), to create second chip subassemblies ((56). At least a portion of at least some of the second chip subassemblies are encapsulated, such as with molding compound (58), to create semiconductor chip packages (60).Type: ApplicationFiled: October 29, 2004Publication date: September 22, 2005Applicant: ChipPAC, Inc.Inventors: Jin-Wook Jeong, In-Sang Yoon, Hee Lee, Hyun-Joon Oh, Hyeog Kwon, Jong Ju, Sang Lee
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Publication number: 20050208700Abstract: A semiconductor chip packaging method (34) includes printing an adhesive (46) on a support surface (42), typically a surface of a semiconductor substrate (44), to create individual adhesive areas (40). Semiconductor chips (24) are individually placed on the individual adhesive areas thereby securing the semiconductor chips to the support surface to create first chip subassemblies (55). The semiconductor chip and the semiconductor substrate are electrically connected to create second chip subassemblies (62). At least a portion of each of at least some of the second chip subassemblies is encapsulated to create semiconductor chip packages (64). The adhesive at the individual adhesive areas is preferably a B-staged adhesive so that solvent is removed from the adhesive before the individually placing step.Type: ApplicationFiled: October 15, 2004Publication date: September 22, 2005Applicant: ChipPAC, Inc.Inventors: Hyeog Kwon, Sang Lee, Jong Ju