Patents by Inventor Hyeok-Sang Oh
Hyeok-Sang Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11600569Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.Type: GrantFiled: April 14, 2021Date of Patent: March 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
-
Publication number: 20210233860Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.Type: ApplicationFiled: April 14, 2021Publication date: July 29, 2021Inventors: SU-HYUN BARK, SANG-HOON AHN, YOUNG-BAE KIM, HYEOK-SANG OH, WOO-JIN LEE, HOON-SEOK SEO, SUNG-JIN KANG
-
Patent number: 11049810Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.Type: GrantFiled: June 21, 2019Date of Patent: June 29, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
-
Patent number: 10916437Abstract: Provided herein is a method of forming micropatterns, including: forming an etching target film on a substrate; forming a photosensitivity assisting layer on the etching target film, the photosensitivity assisting layer being terminated with a hydrophilic group; forming an adhesive layer on the photosensitivity assisting layer, the adhesive layer forming a covalent bond with the hydrophilic group; forming a hydrophobic photoresist film on the adhesive layer; and patterning the photoresist film.Type: GrantFiled: December 27, 2018Date of Patent: February 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Shin Jang, Jong-Min Baek, Hoon-Seok Seo, Eui-Bok Lee, Sung-Jin Kang, Vietha Nguyen, Deok-Young Jung, Sang-Hoon Ahn, Hyeok-Sang Oh, Woo-Kyung You
-
Patent number: 10847454Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.Type: GrantFiled: December 16, 2019Date of Patent: November 24, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Eui Bok Lee, Deok Young Jung, Sang Bom Kang, Doo-Hwan Park, Jong Min Baek, Sang Hoon Ahn, Hyeok Sang Oh, Woo Kyung You
-
Publication number: 20200118926Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Eui Bok LEE, Deok Young JUNG, Sang Bom KANG, Doo-Hwan PARK, Jong Min BAEK, Sang Hoon AHN, Hyeok Sang OH, Woo Kyung YOU
-
Patent number: 10535600Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.Type: GrantFiled: May 23, 2018Date of Patent: January 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoon Seok Seo, Jong Min Baek, Su Hyun Bark, Sang Hoon Ahn, Hyeok Sang Oh, Eui Bok Lee
-
Patent number: 10510658Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.Type: GrantFiled: July 19, 2018Date of Patent: December 17, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Eui Bok Lee, Deok Young Jung, Sang Bom Kang, Doo-Hwan Park, Jong Min Baek, Sang Hoon Ahn, Hyeok Sang Oh, Woo Kyung You
-
Patent number: 10497649Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.Type: GrantFiled: December 5, 2017Date of Patent: December 3, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
-
Patent number: 10475739Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.Type: GrantFiled: December 13, 2017Date of Patent: November 12, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Woo Kyung You, Eui Bok Lee, Jong Min Baek, Su Hyun Bark, Jang Ho Lee, Sang Hoon Ahn, Hyeok Sang Oh
-
Patent number: 10461027Abstract: A semiconductor device includes a lower insulating layer disposed on a substrate. A conductive pattern is formed in the lower insulating layer. A middle insulating layer is disposed on the lower insulating layer and the conductive pattern. A via control region is formed in the middle insulating layer. An upper insulating layer is disposed on the middle insulating layer and the via control region. A via plug is formed to pass through the via control region and to be connected to the conductive pattern. The via control region has a lower etch rate than the middle insulating layer.Type: GrantFiled: June 14, 2018Date of Patent: October 29, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eui Bok Lee, Jong Min Baek, Sang Hoon Ahn, Hyeok Sang Oh
-
Publication number: 20190311992Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.Type: ApplicationFiled: June 21, 2019Publication date: October 10, 2019Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
-
Publication number: 20190304903Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.Type: ApplicationFiled: June 19, 2019Publication date: October 3, 2019Inventors: Woo Kyung YOU, Eui Bok LEE, Jong Min BAEK, Su Hyun BARK, Jang Ho LEE, Sang Hoon AHN, Hyeok Sang OH
-
Publication number: 20190244896Abstract: A semiconductor device includes a lower insulating layer disposed on a substrate. A conductive pattern is formed in the lower insulating layer. A middle insulating layer is disposed on the lower insulating layer and the conductive pattern. A via control region is formed in the middle insulating layer. An upper insulating layer is disposed on the middle insulating layer and the via control region. A via plug is formed to pass through the via control region and to be connected to the conductive pattern. The via control region has a lower etch rate than the middle insulating layer.Type: ApplicationFiled: June 14, 2018Publication date: August 8, 2019Inventors: Eui Bok LEE, Jong Min BAEK, Sang Hoon AHN, Hyeok Sang OH
-
Publication number: 20190198342Abstract: Provided herein is a method of forming micropatterns, including: forming an etching target film on a substrate; forming a photosensitivity assisting layer on the etching target film, the photosensitivity assisting layer being terminated with a hydrophilic group; forming an adhesive layer on the photosensitivity assisting layer, the adhesive layer forming a covalent bond with the hydrophilic group; forming a hydrophobic photoresist film on the adhesive layer; and patterning the photoresist film.Type: ApplicationFiled: December 27, 2018Publication date: June 27, 2019Inventors: SANG-SHIN JANG, JONG-MIN BAEK, HOON-SEOK SEO, EUI-BOK LEE, SUNG-JIN KANG, VIETHA NGUYEN, DEOK-YOUNG JUNG, SANG-HOON AHN, HYEOK-SANG OH, WOO-KYUNG YOU
-
Publication number: 20190181088Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.Type: ApplicationFiled: July 19, 2018Publication date: June 13, 2019Inventors: Eui Bok Lee, Deok Young JUNG, Sang Bom KANG, Doo-Hwan PARK, Jong Min BAEK, Sang Hoon AHN, Hyeok Sang OH, Woo Kyung YOU
-
Publication number: 20190148289Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.Type: ApplicationFiled: May 23, 2018Publication date: May 16, 2019Inventors: Hoon Seok SEO, Jong Min BAEK, Su Hyun BARK, Sang Hoon AHN, Hyeok Sang OH, Eui Bok LEE
-
Patent number: 10276505Abstract: An integrated circuit (IC) device includes a lower wiring structure including a lower metal film. The lower wiring structure penetrates at least a portion of a first insulating film disposed over a substrate. The IC device further includes a capping layer covering a top surface of the lower metal film, a second insulating film covering the capping layer, an upper wiring structure penetrating the second insulating film and the capping layer, and electrically connected to the lower metal film, and an air gap disposed between the lower metal film and the second insulating film. The air gap has a width defined by a distance between the capping layer and the upper wiring structure.Type: GrantFiled: December 19, 2017Date of Patent: April 30, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Bae Kim, Sang-Hoon Ahn, Eui-Bok Lee, Su-Hyun Bark, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
-
Patent number: 10229876Abstract: A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.Type: GrantFiled: March 17, 2016Date of Patent: March 12, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Jung Kim, Young-Bae Kim, Jong-Sam Kim, Jin-Hyeung Park, Jeong-Hoon Ahn, Hyeok-Sang Oh, Kyoung-Woo Lee, Hyo-Seon Lee, Suk-Hee Jang
-
Publication number: 20190043803Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.Type: ApplicationFiled: December 13, 2017Publication date: February 7, 2019Inventors: Woo Kyung YOU, Eui Bok LEE, Jong Min BAEK, Su Hyun BARK, Jang Ho LEE, Sang Hoon AHN, Hyeok Sang OH