Patents by Inventor Hyeon Jun BAEK

Hyeon Jun BAEK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11949012
    Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: April 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Ho Park, Wan Don Kim, Weon Hong Kim, Hyeon Jun Baek, Byoung Hoon Lee, Jeong Hyuk Yim, Sang Jin Hyun
  • Publication number: 20210119058
    Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.
    Type: Application
    Filed: December 8, 2020
    Publication date: April 22, 2021
    Inventors: Jong Ho PARK, Wan Don KIM, Weon Hong KIM, Hyeon Jun BAEK, Byoung Hoon LEE, Jeong Hyuk YIM, Sang Jin HYUN
  • Patent number: 10879392
    Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Ho Park, Wan Don Kim, Weon Hong Kim, Hyeon Jun Baek, Byoung Hoon Lee, Jeong Hyuk Yim, Sang Jin Hyun
  • Publication number: 20200013897
    Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack. includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.
    Type: Application
    Filed: June 25, 2019
    Publication date: January 9, 2020
    Inventors: JONG HO PARK, Wan Don KIM, Weon Hong KIM, Hyeon Jun BAEK, Byoung Hoon LEE, Jeong Hyuk YIM, Sang Jin HYUN