Patents by Inventor Hyo-Cheon Kang
Hyo-Cheon Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9165354Abstract: Methods of analyzing photolithography processes are provided. The methods may include obtaining an image from a pattern formed on a wafer and obtaining dimensions of the image. The methods may further include converting the dimensions into a profile graph and then dividing the profile graph into a low-frequency band profile graph and a high-frequency band profile graph.Type: GrantFiled: June 3, 2013Date of Patent: October 20, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Woong-Kyu Son, Hyo-Cheon Kang, Deok-Yong Kim, Jae-Kwan Park, Jeong-Ho Ahn, Soo-Bok Chin
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Publication number: 20140037186Abstract: Methods of analyzing photolithography processes are provided. The methods may include obtaining an image from a pattern formed on a wafer and obtaining dimensions of the image. The methods may further include converting the dimensions into a profile graph and then dividing the profile graph into a low-frequency band profile graph and a high-frequency band profile graph.Type: ApplicationFiled: June 3, 2013Publication date: February 6, 2014Inventors: Woong-Kyu Son, Hyo-Cheon Kang, Deok-Yong Kim, Jae-Kwan Park, Jeong-Ho Ahn, Soo-Bok Chin
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Patent number: 7398178Abstract: In a method of calculating irregularities of a hole, a center coordinate of an actual hole is set. Inner wall coordinates of the actual hole are obtained from the center coordinate of the actual hole. An area of the actual hole is determined based on the inner wall coordinates of the actual hole. A radius of a virtual hole is determined based on the area of the actual hole. A center coordinate of the virtual hole is determined based on the inner wall coordinates of the actual hole to obtain a circumference line of the virtual hole. A standard deviation of the inner wall coordinates of the actual hole relative to the circumference line of the virtual hole is calculated, thereby obtaining the irregularities of the actual hole.Type: GrantFiled: September 29, 2004Date of Patent: July 8, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Hyo-Cheon Kang
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Patent number: 7126357Abstract: Disclosed are a method and apparatus for inspecting a wafer for electrical defects. A first electron beam is irradiated onto an area of the wafer including an inspection region to charge the area. A second electron beam is irradiated onto the inspection region to inspect the inspection region after focusing the second electron beam on the inspection region. A third electron beam is irradiated onto the area to discharge charges accumulated on the area. Therefore, the electrical defect of the wafer can be precisely detected with increased voltage contrasts for distinguishing the electrical defect. This method and apparatus have improved detection sensitivity and detection reliability over conventional methods.Type: GrantFiled: April 6, 2005Date of Patent: October 24, 2006Assignee: Samsung Electronics Co., Ltd.Inventor: Hyo-Cheon Kang
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Publication number: 20060029286Abstract: An image processing method is disclosed. The method comprises capturing a plurality of images of a sample using a scanning electron microscope (SEM). The method further comprising computing a mean value for each pixel location in the plurality of images and forming an integrated image with the mean values. The method further comprises filtering the integrated image using a median filter.Type: ApplicationFiled: August 8, 2005Publication date: February 9, 2006Inventors: Jung-Taek Lim, Hyo-Cheon Kang, Chung-Sam Jun, Dong-Chun Lee, Byoung-Ho Lee
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Publication number: 20050176159Abstract: Disclosed are a method and apparatus for inspecting a wafer for electrical defects. A first electron beam is irradiated onto an area of the wafer including an inspection region to charge the area. A second electron beam is irradiated onto the inspection region to inspect the inspection region after focusing the second electron beam on the inspection region. A third electron beam is irradiated onto the area to discharge charges accumulated on the area. Therefore, the electrical defect of the wafer can be precisely detected with increased voltage contrasts for distinguishing the electrical defect. This method and apparatus have improved detection sensitivity and detection reliability over conventional methods.Type: ApplicationFiled: April 6, 2005Publication date: August 11, 2005Applicant: Samsung Electronics Co., Ltd.Inventor: Hyo-Cheon Kang
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Patent number: 6913939Abstract: Disclosed are a method and apparatus for inspecting a wafer for electrical defects. A first electron beam is irradiated onto an area of the wafer including an inspection region to charge the area. A second electron beam is irradiated onto the inspection region to inspect the inspection region after focusing the second electron beam on the inspection region. A third electron beam is irradiated onto the area to discharge charges accumulated on the area. Therefore, the electrical defect of the wafer can be precisely detected with increased voltage contrasts for distinguishing the electrical defect. This method and apparatus have improved detection sensitivity and detection reliability over conventional methods.Type: GrantFiled: December 31, 2003Date of Patent: July 5, 2005Assignee: Samsung Electronics Co., Ltd.Inventor: Hyo-Cheon Kang
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Publication number: 20050090999Abstract: In a method of calculating irregularities of a hole, a center coordinate of an actual hole is set. Inner wall coordinates of the actual hole are obtained from the center coordinate of the actual hole. An area of the actual hole is determined based on the inner wall coordinates of the actual hole. A radius of a virtual hole is determined based on the area of the actual hole. A center coordinate of the virtual hole is determined based on the inner wall coordinates of the actual hole to obtain a circumference line of the virtual hole. A standard deviation of the inner wall coordinates of the actual hole relative to the circumference line of the virtual hole is calculated, thereby obtaining the irregularities of the actual hole.Type: ApplicationFiled: September 29, 2004Publication date: April 28, 2005Inventor: Hyo-Cheon Kang
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Publication number: 20040161866Abstract: Disclosed are a method and apparatus for inspecting a wafer for electrical defects. A first electron beam is irradiated onto an area of the wafer including an inspection region to charge the area. A second electron beam is irradiated onto the inspection region to inspect the inspection region after focusing the second electron beam on the inspection region. A third electron beam is irradiated onto the area to discharge charges accumulated on the area. Therefore, the electrical defect of the wafer can be precisely detected with increased voltage contrasts for distinguishing the electrical defect. This method and apparatus have improved detection sensitivity and detection reliability over conventional methods.Type: ApplicationFiled: December 31, 2003Publication date: August 19, 2004Inventor: Hyo-Cheon Kang
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Patent number: 6545491Abstract: The present invention provides apparatus and methods for detecting defects in a semiconductor device. The semiconductor device includes a plurality of conductive pads, which may be formed, for example, between insulating layers for insulating the conductive pads from conductive lines formed between ones of the conductive pads. Electrons and/or holes are accumulated in ones of the conductive pads, for example, on the surface of the conductive pads. A contrast associated with one of the conductive pads is detected based on secondary electron emissions from the ones of the conductive pads after accumulation of the electrons and/or holes. The presence of defects is determined based on the detected contrast.Type: GrantFiled: August 28, 2001Date of Patent: April 8, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Yang-hyong Kim, Hyo-cheon Kang, Deok-yong Kim
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Patent number: 6525318Abstract: Methods of inspecting integrated circuit substrates include the steps of directing a beam of electrons into a first conductive plug located within a first contact hole on an integrated circuit substrate and then measuring a quantity of electrons emitted from the first conductive plug to determine an absence or presence of an electrically insulating residue in the first contact hole. The quantity of electrons emitted from the first conductive plug by secondary electron emission can be measured in order to determine whether electrons are being accumulated within the conductive plug because an insulating residue is blocking passage of the electrons into an underlying conductive portion of the substrate. If an electrically insulating residue is present, then sufficient repulsive forces between the accumulated electrons will result in the secondary emission of excess electrons from an upper surface of the conductive plug as the conductive plug is being irradiated with the electron beam.Type: GrantFiled: August 27, 1999Date of Patent: February 25, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Yang hyong Kim, Hyo-cheon Kang, Deok-yong Kim, Sang-myun Lee
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Publication number: 20020043628Abstract: The present invention provides apparatus and methods for detecting defects in a semiconductor device. The semiconductor device includes a plurality of conductive pads, which may be formed, for example, between insulating layers for insulating the conductive pads from conductive lines formed between ones of the conductive pads. Electrons and/or holes are accumulated in ones of the conductive pads, for example, on the surface of the conductive pads. A contrast associated with one of the conductive pads is detected based on secondary electron emissions from the ones of the conductive pads after accumulation of the electrons and/or holes. The presence of defects is determined based on the detected contrast.Type: ApplicationFiled: August 28, 2001Publication date: April 18, 2002Inventors: Yang-Hyong Kim, Hyo-Cheon Kang, Deok-Yong Kim
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Patent number: 6100102Abstract: A method of in-line monitoring for shallow pits formed on a semiconductor substrate using an electron beam. The electron beam is scanned across exposed pads on the semiconductor substrate and relative concentrations of secondary electrodes are examined to identify shallow pits.Type: GrantFiled: March 10, 1999Date of Patent: August 8, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Yang-hyong Kim, Chun-ha Hwang, Hyo-cheon Kang, Deok-yong Kim