Patents by Inventor Hyo-Jeong Moon

Hyo-Jeong Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960159
    Abstract: Provided are a polyamideimide film, a window cover film, and a display panel including the same. More specifically, a polyamideimide film including an amideimide structure derived from a dianhydride, a diamine, and an aromatic diacid dichloride is provided, wherein a chlorine content in the film is 5 to 33 ppm and a yellow index change amount ?YI is 5 or less, the yellow index change amount being measured in accordance with ASTM E313 after repeating a process of irradiating 0.55 W/m2 of UVA at 340 nm at 40° C. for 20 hours and then blocking UVA for 4 hours three times.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: April 16, 2024
    Assignees: SK Innovation Co., Ltd., SK ie technology Co., Ltd.
    Inventors: Hyeon Jeong Kim, Hye Ri Kim, Se Rah Moon, Sang Yoon Park, Hyo Shin Kwak
  • Patent number: 11557513
    Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon Keun Kim, Jae Wha Park, Jun Kwan Kim, Hyo Jeong Moon, Seung Jong Park, Seul Gi Bae
  • Publication number: 20210242079
    Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.
    Type: Application
    Filed: March 29, 2021
    Publication date: August 5, 2021
    Inventors: Moon Keun KIM, Jae Wha PARK, Jun Kwan KIM, Hyo Jeong MOON, Seung Jong PARK, Seul Gi BAE
  • Patent number: 10971395
    Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: April 6, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon Keun Kim, Jae Wha Park, Jun Kwan Kim, Hyo Jeong Moon, Seung Jong Park, Seul Gi Bae
  • Publication number: 20200027783
    Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.
    Type: Application
    Filed: February 8, 2019
    Publication date: January 23, 2020
    Inventors: Moon Keun KIM, Jae Wha PARK, Jun Kwan KIM, Hyo Jeong MOON, Seung Jong PARK, Seul Gi BAE
  • Patent number: 9281240
    Abstract: In a method of manufacturing a semiconductor device, an insulating interlayer is formed on a substrate. The insulating interlayer is partially removed to form an opening. A barrier conductive layer is formed on a sidewall and a bottom of the opening. An RF sputtering process and a DC sputtering process are performed independently on the barrier conductive layer to form a seed layer. A plated layer is formed on the seed layer.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-Jeong Moon, Woo-Choel Noh, Woo-Jin Jang, Hun Kim, Hong-Jae Shin
  • Publication number: 20150255336
    Abstract: In a method of manufacturing a semiconductor device, an insulating interlayer is formed on a substrate. The insulating interlayer is partially removed to form an opening. A barrier conductive layer is formed on a sidewall and a bottom of the opening. An RF sputtering process and a DC sputtering process are performed independently on the barrier conductive layer to form a seed layer. A plated layer is formed on the seed layer.
    Type: Application
    Filed: March 2, 2015
    Publication date: September 10, 2015
    Inventors: Hyo-Jeong Moon, Woo-Cheol Noh, Woo-Jin Jang, Hun Kim, Hong-Jae Shin