Patents by Inventor Hyo-Joo Ahn
Hyo-Joo Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8120986Abstract: A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.Type: GrantFiled: May 24, 2010Date of Patent: February 21, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Jong Kim, Ho-Cheol Lee, Kyoung-Hwan Kwon, Hyong-Ryol Hwang, Hyo-Joo Ahn
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Publication number: 20100232249Abstract: A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.Type: ApplicationFiled: May 24, 2010Publication date: September 16, 2010Inventors: Nam-Jong Kim, Ho-Cheol Lee, Kyoung-Hwan Kwon, Hyong-Ryol Hwang, Hyo-Joo Ahn
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Patent number: 7768853Abstract: A semiconductor memory device includes: a substrate with first and second memory-cell array regions disposed on first and second substrate sides and first and second sense-circuit regions disposed on the first and second substrate sides between the first and second memory-cell array regions; first and second bitlines coupled to a plurality of memory cells in the first memory-cell array region; first and second complementary bitlines coupled to a plurality of memory cells in the second memory-cell array region; first and second column-selection transistors formed in the first sense-circuit region, and selectively couple the first bitline and the first complementary bitline to a first input/output (I/O) line and a first complementary I/O line; and third and fourth column-selection transistors formed in the second sense-circuit region, and selectively couple the second bitline and the second complementary bitline to a second I/O line and a second complementary I/O line.Type: GrantFiled: March 31, 2008Date of Patent: August 3, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo-Joo Ahn, Kyu-Chan Lee, Chul-Woo Yi
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Patent number: 7596666Abstract: A multi-path accessible semiconductor memory device having a shared memory area in a DRAM memory cell array that can be randomly accessed by a plurality of processors is provided. The multi-path accessible semiconductor memory device includes at least one shared memory area allocated in a memory cell array, operably connected to ports corresponding to a plurality of processors, each port used by the corresponding processor to selective access the shared memory area. The device further comprises an occupancy state signaling unit to output port occupancy state information to the processor requesting access to the shared memory area through the port used for the access request to indicate whether access to the shared memory area is allowed.Type: GrantFiled: August 22, 2006Date of Patent: September 29, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo-Joo Ahn, Chi-Sung Oh
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Patent number: 7586339Abstract: An output circuit and method thereof. In an example, the output circuit may include an output buffer configured to buffer output data and to transfer the buffered output data to an output node, the output buffer initializing the output node in response to a triggering signal. In another example, the method may include buffering output data in response to an output buffer enabling signal, transferring the buffered output data to an output node and initializing the output node of an output buffer in response to a triggering signal.Type: GrantFiled: May 10, 2006Date of Patent: September 8, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Chi-Sung Oh, Hyo-Joo Ahn
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Publication number: 20090175114Abstract: A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.Type: ApplicationFiled: March 11, 2009Publication date: July 9, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam-Jong KIM, Ho-Cheol LEE, Kyoung-Hwan KWON, Hyong-Ryol HWANG, Hyo-Joo AHN
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Patent number: 7505353Abstract: A multi-port semiconductor memory device having variable access paths and a method therefore are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.Type: GrantFiled: August 22, 2006Date of Patent: March 17, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Jong Kim, Ho-Cheol Lee, Kyoung-Hwan Kwon, Hyong-Ryol Hwang, Hyo-Joo Ahn
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Patent number: 7499364Abstract: A multi-port semiconductor memory device and a signal input/output method therefore are provided. In one embodiment, the multi-port semiconductor memory device includes a plurality of different input/output ports and a memory array. The memory array has at least one memory region that is accessed by using different input/output ports. The different input/output ports include a first input/output port through which a first signal is input/output and a second input/output port through which a second signal different from the first signal is input/output. The memory region is divided into a plurality of memory regions. The invention provides effects of reducing the number of test pins and improving test efficiency.Type: GrantFiled: August 22, 2006Date of Patent: March 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo-Joo Ahn, Nam-Jong Kim
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Publication number: 20080298111Abstract: A semiconductor memory device includes: a substrate with first and second memory-cell array regions disposed on first and second substrate sides and first and second sense-circuit regions disposed on the first and second substrate sides between the first and second memory-cell array regions; first and second bitlines coupled to a plurality of memory cells in the first memory-cell array region; first and second complementary bitlines coupled to a plurality of memory cells in the second memory-cell array region; first and second column-selection transistors formed in the first sense-circuit region, and selectively couple the first bitline and the first complementary bitline to a first input/output (I/O) line and a first complementary I/O line; and third and fourth column-selection transistors formed in the second sense-circuit region, and selectively couple the second bitline and the second complementary bitline to a second I/O line and a second complementary I/O line.Type: ApplicationFiled: March 31, 2008Publication date: December 4, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Hyo-Joo Ahn, Kyu-Chan Lee, Chul-Woo Yi
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Publication number: 20070195633Abstract: A multi-port semiconductor memory device and a signal input/output method therefore are provided. In one embodiment, the multi-port semiconductor memory device includes a plurality of different input/output ports and a memory array. The memory array has at least one memory region that is accessed by using different input/output ports. The different input/output ports include a first input/output port through which a first signal is input/output and a second input/output port through which a second signal different from the first signal is input/output. The memory region is divided into a plurality of memory regions. The invention provides effects of reducing the number of test pins and improving test efficiency.Type: ApplicationFiled: August 22, 2006Publication date: August 23, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo-Joo AHN, Nam-Jong KIM
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Publication number: 20070150669Abstract: A multi-path accessible semiconductor memory device having a shared memory area in a DRAM memory cell array that can be randomly accessed by a plurality of processors is provided. The multi-path accessible semiconductor memory device includes at least one shared memory area allocated in a memory cell array, operably connected to ports corresponding to a plurality of processors, each port used by the corresponding processor to selective access the shared memory area. The device further comprises an occupancy state signaling unit to output port occupancy state information to the processor requesting access to the shared memory area through the port used for the access request to indicate whether access to the shared memory area is allowed.Type: ApplicationFiled: August 22, 2006Publication date: June 28, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo-Joo AHN, Chi-Sung OH
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Publication number: 20070147162Abstract: A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.Type: ApplicationFiled: August 22, 2006Publication date: June 28, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam-Jong KIM, Ho-Cheol LEE, Kyoung-Hwan KWON, Hyong-Ryol HWANG, Hyo-Joo AHN
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Publication number: 20070008787Abstract: An output circuit and method thereof. In an example, the output circuit may include an output buffer configured to buffer output data and to transfer the buffered output data to an output node, the output buffer initializing the output node in response to a triggering signal. In another example, the method may include buffering output data in response to an output buffer enabling signal, transferring the buffered output data to an output node and initializing the output node of an output buffer in response to a triggering signal.Type: ApplicationFiled: May 10, 2006Publication date: January 11, 2007Inventors: Chi-Sung Oh, Hyo-Joo Ahn
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Patent number: 6813175Abstract: An interconnection layout includes alternately arranged data-read lines and data-write lines. The data-write lines are maintained at a ground voltage level when the data-read lines in a transitional state, and the data-read lines are maintained at the ground voltage level when the data-write lines in a transitional state. Therefore, a coupling capacitance is not produced between adjacent data-write lines and adjacent data-read lines.Type: GrantFiled: September 25, 2002Date of Patent: November 2, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo-Joo Ahn, Byong-Mo Moon, Hyun-Kyoung Kim
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Publication number: 20030058677Abstract: An interconnection layout includes alternately arranged data-read lines and data-write lines. The data-write lines are maintained at a ground voltage level when the data-read lines in a transitional state, and the data-read lines are maintained at the ground voltage level when the data-write lines in a transitional state. Therefore, a coupling capacitance is not produced between adjacent data-write lines and adjacent data-read lines.Type: ApplicationFiled: September 25, 2002Publication date: March 27, 2003Inventors: Hyo-Joo Ahn, Byong-Mo Moon, Hyun-Kyoung Kim