Abstract: An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.

Abstract: Disclosed is an invention relating to a processor-executed method for outputting a hierarchical command menu on a display depending on user inputs.

Abstract: Disclosed is an invention relating to a processor-executed method for outputting a hierarchical command menu on a display depending on user inputs.

Abstract: An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.

Abstract: An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.

Abstract: Disclosed is an invention relating to a processor-executed method for outputting a hierarchical command menu on a display depending on user inputs.

Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed over the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling a space between adjacent ones of the plurality of memory cells; and a second insulating layer disposed over the first insulating layer. The first insulating layer has a dielectric constant smaller than that of the second insulating layer, a thermal conductivity smaller than that of the second insulating layer, or both.

Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.

Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed over the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling a space between adjacent ones of the plurality of memory cells; and a second insulating layer disposed over the first insulating layer. The first insulating layer has a dielectric constant smaller than that of the second insulating layer, a thermal conductivity smaller than that of the second insulating layer, or both.

Abstract: An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.

Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.

Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.

Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.

Abstract: A semiconductor memory may include: a first stacked structure including a first word line disposed over a substrate and extended in a first direction, a first bit line disposed over the first word line and extended in a second direction crossing the first direction, and a first variable resistance layer interposed between the first word line and the first bit line; and a second stacked structure including a second bit line disposed over the first stacked structure and extended in the second direction, a second word line disposed over the second bit line and extended in the first direction, and a second variable resistance layer interposed between the second word line and the second bit line; and a first selecting element layer interposed between the first bit line and the second bit line.

Abstract: A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers.

Abstract: A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers.

Abstract: A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers.

Abstract: According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern.

Abstract: A semiconductor memory may include: a first stacked structure including a first word line disposed over a substrate and extended in a first direction, a first bit line disposed over the first word line and extended in a second direction crossing the first direction, and a first variable resistance layer interposed between the first word line and the first bit line; and a second stacked structure including a second bit line disposed over the first stacked structure and extended in the second direction, a second word line disposed over the second bit line and extended in the first direction, and a second variable resistance layer interposed between the second word line and the second bit line; and a first selecting element layer interposed between the first bit line and the second bit line.

Abstract: According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern.