Abstract: A sandwich panel for an automobile includes a core layer, a surface layer, and an adhesive layer. The core layer includes glass fibers and thermoplastic resins and defines an optimal weight and thickness to provide flexural performance and non-flammability. The sandwich panel provides a flame barrier layer, which is a non-combustible layer during ignition and prevents flame from leaking to the outside of the panel.

Abstract: System on chip including plurality of processors including first and second processors; plurality of intellectual properties (IPs) including first and second IPs; memory interface; internal clock circuit to receive reference clock signal, generate first internal clock signal, and provide first internal clock signal to first IP; memory interface clock circuit to receive reference clock signal, generate memory interface clock signal, and provide memory interface clock signal to memory interface; and power management unit (PMU), wherein first internal clock signal drives first IP, memory interface clock signal drives memory interface, PMU generates first control signal based on operational states of plurality of processors, and provides first control signal to internal clock circuit, PMU generates second control signal based on operational states of plurality of processors, and provides second control signal to memory interface clock circuit, internal clock circuit sets clock rate of first internal clock signal

Abstract: System on chip including plurality of processors including first and second processors; plurality of intellectual properties (IPs) including first and second IPs; memory interface; internal clock circuit to receive reference clock signal, generate first internal clock signal, and provide first internal clock signal to first IP; memory interface clock circuit to receive reference clock signal, generate memory interface clock signal, and provide memory interface clock signal to memory interface; and power management unit (PMU), wherein first internal clock signal drives first IP, memory interface clock signal drives memory interface, PMU generates first control signal based on operational states of plurality of processors, and provides first control signal to internal clock circuit, PMU generates second control signal based on operational states of plurality of processors, and provides second control signal to memory interface clock circuit, internal clock circuit sets clock rate of first internal clock signal

Abstract: System on chip including plurality of processors including first and second processors; plurality of intellectual properties (IPs) including first and second IPs; memory interface; internal clock circuit to receive reference clock signal, generate first internal clock signal, and provide first internal clock signal to first IP; memory interface clock circuit to receive reference clock signal, generate memory interface clock signal, and provide memory interface clock signal to memory interface; and power management unit (PMU), wherein first internal clock signal drives first IP, memory interface clock signal drives memory interface, PMU generates first control signal based on operational states of plurality of processors, and provides first control signal to internal clock circuit, PMU generates second control signal based on operational states of plurality of processors, and provides second control signal to memory interface clock circuit, internal clock circuit sets clock rate of first internal clock signal

Abstract: System on chip including plurality of processors including first and second processors; plurality of intellectual properties (IPs) including first and second IPs; memory interface; internal clock circuit to receive reference clock signal, generate first internal clock signal, and provide first internal clock signal to first IP; memory interface clock circuit to receive reference clock signal, generate memory interface clock signal, and provide memory interface clock signal to memory interface; and power management unit (PMU), wherein first internal clock signal drives first IP, memory interface clock signal drives memory interface, PMU generates first control signal based on operational states of plurality of processors, and provides first control signal to internal clock circuit, PMU generates second control signal based on operational states of plurality of processors, and provides second control signal to memory interface clock circuit, internal clock circuit sets clock rate of first internal clock signal

Abstract: Systems, apparatuses, and methods of power management for a system on a chip (SoC) are described. In one method, the operational states of the cores/processors of the SoC are monitored and, if a core/processor is in idle or standby mode, the rate of the clock signal driving a component, such as a memory interface, associated with the idle core/processor is reduced, thereby reducing power consumption.

Abstract: Systems, apparatuses, and methods of power management for a system on a chip (SoC) are described. In one method, the operational states of the cores/processors of the SoC are monitored and, if a core/processor is in idle or standby mode, the rate of the clock signal driving a component, such as a memory interface, associated with the idle core/processor is reduced, thereby reducing power consumption.

Abstract: A control system for a semiconductor processing apparatus comprises a control server connected to a semiconductor processing apparatus, a verification server connected to the control server, and a database connected to the verification server. The verification server evaluates input parameter values stored in the semiconductor processing apparatus against verification data stored in the database. The results of the evaluation are used to determine whether a process will be performed by the semiconductor processing apparatus.

Abstract: A control system for a semiconductor processing apparatus comprises a control server connected to a semiconductor processing apparatus, a verification server connected to the control server, and a database connected to the verification server. The verification server evaluates input parameter values stored in the semiconductor processing apparatus against verification data stored in the database. The results of the evaluation are used to determine whether a process will be performed by the semiconductor processing apparatus.

Abstract: An ion implantation apparatus for integrated circuit manufacturing is disclosed. In an apparatus in accordance with an embodiment of the invention, a current detector detects a current flowing to a turbo pump. A display displays information about the detected current, and a controller determines whether the detected current is within a specified range. If the detected current is not within the specified range, the controller issues a power control signal to, stop the turbo pump. At this time, the controller also stops an ion implantation of the apparatus.

Abstract: A vacuum apparatus of an ion implantation system having an ion generator includes a vacuum pump evacuating the interior of the ion generator, a vacuum line connected between the vacuum pump and the ion generator, at least one first type valve connected to the ion generator and the vacuum line for injecting an inert gas into the ion generator and the vacuum line to equalize internal and external pressures of the ion generator and the vacuum line and to remove the air from the interior of the ion generator and the vacuum line, so that oxygen does not react with an inflammable impurity inside the ion generator, and at least one second type valve connected to the ion generator for being closed or opened to maintain a pressure of the ion generator to a predetermined vacuum level.