Patents by Inventor Hyo Seok Woo

Hyo Seok Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240129725
    Abstract: A service identifying and processing method using a wireless terminal message according to an exemplary embodiment of the present invention includes (a) receiving a wireless terminal message by a first entity which is a mobile device; and (b) expressing, by a first agent which is an information processing application program installed on the first entity, entity information of second entity based on the wireless terminal message and service confirmation information related to service provided by the second entity, through an application screen by the first agent.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 18, 2024
    Applicant: ESTORM CO., LTD.
    Inventors: Jong Hyun WOO, Tae Il LEE, Il Jin JUNG, Hee Jun SHIN, Hyung Seok JANG, Min Jae SON, Sang Heon BAEK, Seo Bin PARK, Hyo Sang KWON, Mi Ju KIM, Jung Hoon SONG, Rakhmanov DILSHOD, Dong Hee KIM, Jeon Gjin KIM
  • Patent number: 10204901
    Abstract: A semiconductor device is provided including a resistor structure on a semiconductor substrate. The resistor structure includes pad portions and a resistor body connecting the pad portions. The pad portions each have a width greater than a width of the resistor body. The pad portions each include a pad pattern and a liner pattern covering a sidewall and a lower surface of the pad pattern. The resistor body extends laterally from the liner pattern. The pad pattern includes a different material from the resistor body and the liner pattern.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo Seok Woo, Jang Gn Yun, Joon Sung Lim, Sung Min Hwang
  • Publication number: 20180254271
    Abstract: A semiconductor device is provided including a resistor structure on a semiconductor substrate. The resistor structure includes pad portions and a resistor body connecting the pad portions. The pad portions each have a width greater than a width of the resistor body. The pad portions each include a pad pattern and a liner pattern covering a sidewall and a lower surface of the pad pattern. The resistor body extends laterally from the liner pattern. The pad pattern includes a different material from the resistor body and the liner pattern.
    Type: Application
    Filed: October 3, 2017
    Publication date: September 6, 2018
    Inventors: Hyo Seok Woo, Jang Gn YUN, Joon Sung LIM, Sung Min HWANG
  • Patent number: 9698066
    Abstract: A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: July 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bo-Ra Lee, Jae-Ho Jeong, Nam-Gyu Baek, Hyo-Seok Woo, Hyun-Sook Yoon, Kwang-Yong Lee
  • Publication number: 20170103929
    Abstract: A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.
    Type: Application
    Filed: July 5, 2016
    Publication date: April 13, 2017
    Inventors: Bo-Ra LEE, Jae-Ho JEONG, Nam-Gyu BAEK, Hyo-Seok WOO, Hyun-Sook YOON, Kwang-Yong LEE
  • Patent number: 9570446
    Abstract: A semiconductor device includes a plurality of semiconductor devices, a plurality of metal lines electrically connected to at least one of the semiconductor devices, and a protective layer on the metal lines. The protective layer includes a plurality of open areas partially exposing the metal lines and which serves as pads. A first pad includes a first area that extends from at least one of the metal lines and at least one second area around and separated from the first area.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo Seok Woo, In Mo Kim, Bora Lee, Sun Young Kim, Hoo Sung Cho