Patents by Inventor HYOTAEK LEEM
HYOTAEK LEEM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940862Abstract: A storage controller communicates with an external device including a submission queue and a completion queue. An operation method of the storage controller includes receiving a notification associated with a command from the external device, based on a first clock, fetching the command from the submission queue, based on a second clock, performing an operation corresponding to the fetched command, based on a third clock, writing completion information to the completion queue, based on a fourth clock, and transmitting an interrupt signal to the external device, based on a fifth clock. Each of the first clock to the fifth clock is selectively activated depending on each operation phase.Type: GrantFiled: January 18, 2021Date of Patent: March 26, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun Ju Yi, Jaeho Sim, Kicheol Eom, Dong-Ryoul Lee, Hyotaek Leem
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Patent number: 11854630Abstract: A storage device is provided which shares a host memory with a host. The storage device includes an interface that exchanges data with the host and implements a protocol to use a partial area of the host memory as a buffer of the storage device. A storage controller of the storage device monitors deterioration information of a first area of the buffer and transmits a corruption prediction notification associated with the first area to the host based on a result of the monitoring.Type: GrantFiled: September 26, 2022Date of Patent: December 26, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Ryoul Lee, Hyun Ju Yi, Jaeho Sim, Kicheol Eom, Hyotaek Leem
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Publication number: 20230020537Abstract: A storage device is provided which shares a host memory with a host. The storage device includes an interface that exchanges data with the host and implements a protocol to use a partial area of the host memory as a buffer of the storage device. A storage controller of the storage device monitors deterioration information of a first area of the buffer and transmits a corruption prediction notification associated with the first area to the host based on a result of the monitoring.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Inventors: DONG-RYOUL LEE, Hyun Ju Yi, Jaeho Sim, Kicheol Eom, Hyotaek Leem
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Patent number: 11501843Abstract: A storage device is provided which shares a host memory with a host. The storage device includes an interface that exchanges data with the host and implements a protocol to use a partial area of the host memory as a buffer of the storage device. A storage controller of the storage device monitors deterioration information of a first area of the buffer and transmits a corruption prediction notification associated with the first area to the host based on a result of the monitoring.Type: GrantFiled: May 4, 2021Date of Patent: November 15, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Ryoul Lee, Hyun Ju Yi, Jaeho Sim, Kicheol Eom, Hyotaek Leem
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Publication number: 20210257034Abstract: A storage device is provided which shares a host memory with a host. The storage device includes an interface that exchanges data with the host and implements a protocol to use a partial area of the host memory as a buffer of the storage device. A storage controller of the storage device monitors deterioration information of a first area of the buffer and transmits a corruption prediction notification associated with the first area to the host based on a result of the monitoring.Type: ApplicationFiled: May 4, 2021Publication date: August 19, 2021Inventors: DONG-RYOUL LEE, HYUN JU YI, JAEHO SIM, KICHEOL EOM, HYOTAEK LEEM
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Publication number: 20210248035Abstract: A storage device sharing a host memory of a host, the storage device includes a serial interface that exchanges data with the host, and a storage controller that stores buffering data in a host memory buffer allocated by the host through the serial interface. The storage controller performs error correction encoding and error correction decoding on the buffering data.Type: ApplicationFiled: April 25, 2021Publication date: August 12, 2021Inventors: KICHEOL EOM, JAEHO SIM, DONG-RYOUL LEE, HYUN JU YI, HYOTAEK LEEM
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Patent number: 11016846Abstract: A storage device sharing a host memory of a host, the storage device includes a serial interface that exchanges data with the host, and a storage controller that stores buffering data in a host memory buffer allocated by the host through the serial interface. The storage controller performs error correction encoding and error correction decoding on the buffering data.Type: GrantFiled: August 7, 2019Date of Patent: May 25, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Kicheol Eom, Jaeho Sim, Dong-Ryoul Lee, Hyun Ju Yi, Hyotaek Leem
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Patent number: 11011243Abstract: A storage device is provided which shares a host memory with a host. The storage device includes an interface that exchanges data with the host and implements a protocol to use a partial area of the host memory as a buffer of the storage device. A storage controller of the storage device monitors deterioration information of a first area of the buffer and transmits a corruption prediction notification associated with the first area to the host based on a result of the monitoring.Type: GrantFiled: August 13, 2019Date of Patent: May 18, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Ryoul Lee, Hyun Ju Yi, Jaeho Sim, Kicheol Eom, Hyotaek Leem
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Publication number: 20210141440Abstract: A storage controller communicates with an external device including a submission queue and a completion queue. An operation method of the storage controller includes receiving a notification associated with a command from the external device, based on a first clock, fetching the command from the submission queue, based on a second clock, performing an operation corresponding to the fetched command, based on a third clock, writing completion information to the completion queue, based on a fourth clock, and transmitting an interrupt signal to the external device, based on a fifth clock. Each of the first clock to the fifth clock is selectively activated depending on each operation phase.Type: ApplicationFiled: January 18, 2021Publication date: May 13, 2021Inventors: HYUN JU YI, JAEHO SIM, KICHEOL EOM, DONG-RYOUL LEE, HYOTAEK LEEM
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Patent number: 10895905Abstract: A storage controller communicates with an external device including a submission queue and a completion queue. An operation method of the storage controller includes receiving a notification associated with a command from the external device, based on a first clock, fetching the command from the submission queue, based on a second clock, performing an operation corresponding to the fetched command, based on a third clock, writing completion information to the completion queue, based on a fourth clock, and transmitting an interrupt signal to the external device, based on a fifth clock. Each of the first clock to the fifth clock is selectively activated depending on each operation phase.Type: GrantFiled: August 6, 2018Date of Patent: January 19, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun Ju Yi, Jaeho Sim, Kicheol Eom, Dong-Ryoul Lee, Hyotaek Leem
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Publication number: 20200151055Abstract: A storage device sharing a host memory of a host, the storage device includes a serial interface that exchanges data with the host, and a storage controller that stores buffering data in a host memory buffer allocated by the host through the serial interface. The storage controller performs error correction encoding and error correction decoding on the buffering data.Type: ApplicationFiled: August 7, 2019Publication date: May 14, 2020Inventors: KICHEOL EOM, JAEHO SIM, DONG-RYOUL LEE, HYUN JU YI, HYOTAEK LEEM
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Publication number: 20200151040Abstract: A storage device is provided which shares a host memory with a host. The storage device includes an interface that exchanges data with the host and implements a protocol to use a partial area of the host memory as a buffer of the storage device. A storage controller of the storage device monitors deterioration information of a first area of the buffer and transmits a corruption prediction notification associated with the first area to the host based on a result of the monitoring.Type: ApplicationFiled: August 13, 2019Publication date: May 14, 2020Inventors: DONG-RYOUL LEE, Hyun Ju Yi, Jaeho Sim, Kicheol Eom, Hyotaek Leem
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Patent number: 10637502Abstract: A storage device includes a nonvolatile memory device and a controller configured to read data from the nonvolatile memory device, to divide the read data into a plurality of segments, and to sequentially perform error correction decoding with respect to the plurality of segments. When the error correction decoding of each segment is completed, the controller adds error correction parity to each of the decoded segments and sends the decoded segments with added error correction parity to an external host device. When error correction decoding of a second segment is not completed after a threshold time has elapsed after sending a first segment of which error correction decoding is completed, the controller adds an incorrect error correction parity to dummy data and sends the dummy data with the added incorrect error correction parity to the external host device.Type: GrantFiled: August 29, 2018Date of Patent: April 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Yongwon Cho, Hyunsoo Bae, Hyotaek Leem, Dong-Ryoul Lee, Hyun Ju YI, Taehack Lee
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Publication number: 20190187774Abstract: A storage controller communicates with an external device including a submission queue and a completion queue. An operation method of the storage controller includes receiving a notification associated with a command from the external device, based on a first clock, fetching the command from the submission queue, based on a second clock, performing an operation corresponding to the fetched command, based on a third clock, writing completion information to the completion queue, based on a fourth clock, and transmitting an interrupt signal to the external device, based on a fifth clock. Each of the first clock to the fifth clock is selectively activated depending on each operation phase.Type: ApplicationFiled: August 6, 2018Publication date: June 20, 2019Inventors: HYUN JU YI, JAEHO SIM, KICHEOL EOM, DONG-RYOUL LEE, HYOTAEK LEEM
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Publication number: 20190036546Abstract: A storage device includes a nonvolatile memory device and a controller configured to read data from the nonvolatile memory device, to divide the read data into a plurality of segments, and to sequentially perform error correction decoding with respect to the plurality of segments. When the error correction decoding of each segment is completed, the controller adds error correction parity to each of the decoded segments and sends the decoded segments with added error correction parity to an external host device. When error correction decoding of a second segment is not completed after a threshold time has elapsed after sending a first segment of which error correction decoding is completed, the controller adds an incorrect error correction parity to dummy data and sends the dummy data with the added incorrect error correction parity to the external host device.Type: ApplicationFiled: August 29, 2018Publication date: January 31, 2019Inventors: YONGWON CHO, HYNSOO BAE, HYOTAEK LEEM, DONG-RYOUL LEE, HYUN JU YI, TAEHACK LEE
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Patent number: 10090858Abstract: A storage device includes a nonvolatile memory device and a controller configured to read data from the nonvolatile memory device, to divide the read data into a plurality of segments, and to sequentially perform error correction decoding with respect to the plurality of segments. When the error correction decoding of each segment is completed, the controller adds error correction parity to each of the decoded segments and sends the decoded segments with added error correction parity to an external host device. When error correction decoding of a second segment is not completed after a threshold time has elapsed after sending a first segment of which error correction decoding is completed, the controller adds an incorrect error correction parity to dummy data and sends the dummy data with the added incorrect error correction parity to the external host device.Type: GrantFiled: December 14, 2016Date of Patent: October 2, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yongwon Cho, Hynsoo Bae, Hyotaek Leem, Dong-Ryoul Lee, Hyun Ju Yi, Taehack Lee
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Patent number: 9886378Abstract: A nonvolatile memory system is provided. The memory system includes a nonvolatile memory device and a memory controller. The memory controller transmits first to fourth control signals to the nonvolatile memory device, sends a command, an address, and input data via a data bus, and receives output data via the data bus. The nonvolatile memory device receives the first to fourth control signals, and recognizes signals received via the data bus at a rising edge or a falling edge of the fourth control signal, as one of the command, the address, and the input data in response to the first to third control signals, and transfers the output data to the memory controller via the data bus based on the fourth control signal.Type: GrantFiled: December 1, 2014Date of Patent: February 6, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Hyotaek Leem
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Publication number: 20170170845Abstract: A storage device includes a nonvolatile memory device and a controller configured to read data from the nonvolatile memory device, to divide the read data into a plurality of segments, and to sequentially perform error correction decoding with respect to the plurality of segments. When the error correction decoding of each segment is completed, the controller adds error correction parity to each of the decoded segments and sends the decoded segments with added error correction parity to an external host device. When error correction decoding of a second segment is not completed after a threshold time has elapsed after sending a first segment of which error correction decoding is completed, the controller adds an incorrect error correction parity to dummy data and sends the dummy data with the added incorrect error correction parity to the external host device.Type: ApplicationFiled: December 14, 2016Publication date: June 15, 2017Inventors: YONGWON CHO, HYNSOO BAE, HYOTAEK LEEM, DONG-RYOUL LEE, HYUN JU YI, TAEHACK LEE
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Publication number: 20150310916Abstract: A nonvolatile memory system is provided. The memory system includes a nonvolatile memory device and a memory controller. The memory controller transmits first to fourth control signals to the nonvolatile memory device, sends a command, an address, and input data via a data bus, and receives output data via the data bus. The nonvolatile memory device receives the first to fourth control signals, and recognizes signals received via the data bus at a rising edge or a falling edge of the fourth control signal, as one of the command, the address, and the input data in response to the first to third control signals, and transfers the output data to the memory controller via the data bus based on the fourth control signal.Type: ApplicationFiled: December 1, 2014Publication date: October 29, 2015Inventor: HYOTAEK LEEM