Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrode, and an image defect area caused by the impurity ions is screened with the black matrix.

Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrode, and an image defect area caused by the impurity ions is screened with the black matrix.

Abstract: A thin film transistor liquid crystal display (TFT-LCD) of a line inversion type for block-driving data lines is provided which can prevent a block defect. In accordance with the feature of the present invention, the TFT-LCD includes an extension part such as an extension piece overlapping with a pixel electrode of boundary pixels at a boundary data line applying a data signal to the boundary pixels.

Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.

Abstract: Disclosed is a low power LCD which comprises a scan signal line for supplying scanning signals to pixels configuring an LCD panel; a source signal line for supplying image signals to pixels configuring an LCD panel; a pixel switch for outputting the image signals to a third electrode from a first electrode connected to the source signal line or stopping the same according to a high or low voltage state of a second electrode connected to the scan signal line; a power unit for respectively supplying first and second powers to all pixels from the outside of a pixel area of the LCD panel; a control signal line unit respectively including a first control signal line for transmitting a first control signal to all pixels from the outside of the pixel area of the LCD panel, and a second control signal line for transmitting a second control signal to all pixels from the outside of the pixel area of the LCD panel; a liquid crystal unit for transmitting or blocking light according to voltage difference between the image

Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.

Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.

Abstract: A nonvolatile semiconductor integrated circuit having a cell array consisting of a plurality of memory strings each having first to N-th (N=2, 3, 4, . . . ) memory cell transistors of a NAND structure includes a plurality of first string select transistors connected in series to the first memory cell transistor, and a plurality of second string select transistors connected in series to the N-th memory cell transistor. One of the string select transistors serially connected to the first and N-th memory cell transistors has a control terminal connected to a ground connecting point, thus to have a ground select function as well as a string select function.

Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.

Abstract: A thin film transistor liquid crystal display (TFT-LCD) of a line inversion type for block-driving data lines is provided which can prevent a block defect. In accordance with the feature of the present invention, the TFT-LCD includes an extension part such as an extension piece overlapping with a pixel electrode of boundary pixels at a boundary data line applying a data signal to the boundary pixels.

Abstract: Disclosed is a low power LCD which comprises a scan signal line for supplying scanning signals to pixels configuring an LCD panel; a source signal line for supplying image signals to pixels configuring an LCD panel; a pixel switch for outputting the image signals to a third electrode from a first electrode connected to the source signal line or stopping the same according to a high or low voltage state of a second electrode connected to the scan signal line; a power unit for respectively supplying first and second powers to all pixels from the outside of a pixel area of the LCD panel; a control signal line unit respectively including a first control signal line for transmitting a first control signal to all pixels from the outside of the pixel area of the LCD panel, and a second control signal line for transmitting a second control signal to all pixels from the outside of the pixel area of the LCD panel; a liquid crystal unit for transmitting or blocking light according to voltage difference between the image

Abstract: Liquid crystal displays include power supply control circuits and methods that are responsive to a single DC input supply voltage, to generate operating voltages for the gate driver, the data driver and the timing converter of the liquid crystal display from the single DC input supply voltage. Preferably, the data driver supply voltage and the gate driver supply voltage are generated prior to generating the gray scale voltage and the gate ON and OFF voltages. Also preferably, the timing converter supply voltage is generated prior to generating the gray voltage and the gate ON and OFF voltages. Accordingly, a single external power supply voltage may be used to generate the requisite supply and operational voltages for the components of the liquid crystal display. Moreover, the sequence of energizing the various components of the liquid crystal display may be automatically controlled, so that improper operation and/or failure of the liquid crystal display can be reduced and preferably prevented.

Abstract: The present invention provides a redundancy circuit in a semiconductor memory device which has spare memory cells which can store information that can be substituted for data of defective memory cells after the completion of the manufacturing process. If addresses designating the defective memory cells are externally input, the redundancy circuit generates a defective cell relief address signal which corresponds to the address designating the defective memory cell and is used to prevent defective data stored in normal memory cells from being output and causes correction data, to be substituted for the defective data output in correspondence with the defective cell relief address.

Abstract: Liquid crystal display devices include an array of liquid crystal display cells arranged as a plurality of columns of display cells electrically coupled to respective data lines and a plurality of rows of display cells electrically coupled to respective gate lines. A gate line on/off voltage generator and gate line driving circuit are provided to drive at least a first gate line with a turn-on voltage of first polarity (e.g., positive voltage) and simultaneously driving at least a second gate line with a turn-off voltage of second polarity (e.g., negative voltage). First and second screen clearing circuits are also provided to improve the screen clearing capability of the liquid crystal display device. The first screen clearing circuit can be electrically coupled to the first gate line to perform the function of driving the first gate line from the turn-on voltage (e.g.

Abstract: A liquid crystal display and method of operating the display includes an array of LCD elements arranged as a plurality of rows and a plurality of columns. A respective one of a plurality of data lines is connected to a respective column of LCD elements. A column of dummy LCD elements is disposed adjacent an outermost column of the array of LCD elements, and a dummy data line is connected to the dummy LCD elements of the column of dummy LCD elements. Preferably, a respective one of the plurality of data lines extends along a side of the column of LCD elements to which it is connected, between the column of LCD elements to which it is connected and an adjacent column of LCD elements, and the dummy data line extends along a side of the column of dummy LCD elements, between the column of dummy elements and the adjacent outermost column of the array of LCD elements.

Abstract: A semiconductor memory includes a plurality of main bit lines led to sense amplifiers and arranged in a row, direction, a first group of sub bit lines interposed between the memory banks and connected to the main bit lines through a first group of selection transistors, and a second group of sub bit lines interposed between the memory banks and the first group of sub bit lines and connected to a common ground line through a second group of selection transistors.

Abstract: Integrated circuit memory devices having direct read capability eliminate the use of page buffers to retain bit line data during reading operations. The page buffer is replaced by a plurality of PMOS pull-up transistors which are coupled through NMOS pass transistors to respective bit lines and also directly to inputs of a column selection circuit. A PMOS pull-up transistor and sense amplifier are also preferably provided at an output of the column selection circuit so that respective bit lines can be read one-at-a-time upon sequential application of a plurality of column address signals to the column selection circuit. The output of the sense amplifier is then provided to an output buffer which is typically electrically connected to an I/O pad.

Abstract: A polysilicon gate electrode of an integrated circuit field effect transistor is formed in two portions which are isolated from one another. The first portion is formed on the gate insulating region. The second portion is formed on the semiconductor substrate outside the gate insulating region and is electrically insulated from the first portion. Since the first and second portions of the polysilicon gate electrode are isolated from one another, only the charge which is on the first polysilicon portion contributes to gate insulating region degradation during plasma etching. After polysilicon gate electrode formation, the first and second portions may be electrically connected by a link. Field effect transistor performance and/or reliability are thereby increased.

Abstract: A semiconductor integrated circuit having an address transition detector includes a power detecting circuit connected to a source terminal for detecting a voltage level of the source terminal, a pulse generating circuit for receiving an address signal and generating a pulse when the address signal is changed, and a summator for combining outputs of the power detecting circuit and the pulse generating circuit and generating a given pulse when the outputs vary.

Abstract: A nonvolatile semiconductor memory with a unit cell structure suitable for high speed operation and a low power supply voltage. The nonvolatile semiconductor memory includes a switching circuit including block select transistors connected by its respective terminal to a corresponding bit line. This switching circuit transmits a signal only when a string to which the switching circuit corresponds is selected. A second active region having a different impurity concentration from a first active region constituting source and drain regions of memory transistors is formed at a substrate contact portion of a bit line contact portion where the memory string and bit line are connected. The impurity concentration of the second active region is lower than that of the first active region.