Abstract: A liquid crystal display (LCD) device, including a lower polarizing plate configured to have a transmission axis in a first direction, a liquid crystal layer on the lower polarizing plate, an upper polarizing plate on the liquid crystal layer, the upper polarizing plate including a first polarizing plate and a second polarizing plate, the first polarizing plate having a transmission axis in the first direction, the second polarizing plate having a transmission axis in a second direction perpendicular to the first direction, and color filters including a white filter and a colored filter, the white filter overlapping with the first polarizing plate, and the color filter overlapping with the second polarizing plate.

Abstract: A curved display device includes a first substrate, a second substrate facing the first substrate, a liquid crystal layer disposed between the first and second substrates, the liquid crystal layer including liquid crystal molecules, a first alignment layer including reactive mesogens which are polymerized with each other, the first alignment layer being disposed between the first substrate and the liquid crystal layer, and a second alignment layer disposed between the liquid crystal layer and the second substrate, where the reactive mesogens have a functional group having charges.

Abstract: A display apparatus includes a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction intersecting the first direction, a plurality of auxiliary gate lines extending in the second direction, a plurality of auxiliary data lines extending in the first direction, a display panel including first pixels and second pixels, and a driving part controlling the display panel to display an image. The first pixels are connected to the plurality of gate lines and the plurality of data lines, respectively. The second pixels are connected to the plurality of auxiliary gate lines and the plurality of auxiliary data lines, respectively. The auxiliary gate lines correspond to the gate lines, respectively. Each of the auxiliary gate lines is electrically connected to the corresponding one of the gate lines.

Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes a first substrate. A first reflection layer is disposed under the first substrate. A first polarization layer is disposed on the first substrate. A light source is disposed at a side of the first substrate. A thin film transistor is disposed on the first polarization layer. A pixel electrode is connected to the thin film transistor. The first polarization layer includes a plurality of wire grid polarization patterns.

Abstract: Provided is an array substrate including a base substrate, a thin film transistor having a semiconductor layer disposed on a first part of the base substrate. The semiconductor layer includes a source electrode and a drain electrode, a gate electrode disposed on the semiconductor layer and insulated from the semiconductor layer. A light-blocking layer disposed between the base substrate and the thin film transistor. The light-blocking layer comprises a first layer continuously disposed on and around the first part of the base substrate, and a second layer formed on the first part of the base substrate without extending outside of the first part, the second layer being disposed on the first layer.

Abstract: A display panel includes a gate line extending substantially in a first direction, a first data line extending in a second direction substantially perpendicular to the first direction and a first switching element comprising a first electrode, a second electrode and a channel layer, where an end portion of the first electrode has a first edge oriented substantially perpendicular to a direction of extension of the first electrode, and the second electrode extends in a direction substantially opposite to the first electrode and an end portion of the second electrode has a second edge oriented substantially perpendicular to a direction of extension of the second electrode, and the channel layer substantially entirely covers both a lower surface of the first electrode and a lower surface of the second electrode.

Abstract: Provided are a display device and a manufacturing method thereof capable of preventing aggregation of an alignment layer and maintaining uniformly a cell-gap. The display device according to an exemplary embodiment of the invention includes: a substrate including a plurality of pixel areas; a thin film transistor formed on the substrate; a pixel electrode connected to the thin film transistor and formed in the pixel area; a barrier layer formed on the pixel electrode; a roof layer formed on the barrier layer to be spaced apart from the barrier layer with a microcavity therebetween; and a liquid crystal formed to fill the microcavity.

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.

Abstract: A light emitting diode (LED), includes: a substrate; a first electrode connection line disposed on the substrate; a second electrode connection line disposed on the substrate; a first contact metal layer disposed on the first electrode connection line; a second contact metal layer disposed on the second electrode connection line; a light emitting unit disposed on the first contact metal layer and the second contact metal layer; a partition disposed on the substrate and about the light emitting unit; and an encapsulation layer covering the light emitting unit. The encapsulation layer includes a light conversion material.

Abstract: RC delay in gate lines of a wide display is reduced by using a low resistivity conductor in the gate lines and a different conductor for forming corresponding gate electrodes. More specifically, a corresponding display substrate includes a gate line made of a first gate line metal, a data line made of a first data line metal, a pixel transistor and a first connection providing part. The pixel transistor includes a first active pattern formed of polycrystalline silicon (poly-Si) and a first gate electrode formed there above and made of a conductive material different from the first gate line metal. The first connection providing part connects the first gate electrode to the gate line. On the other hand, the source electrode is integrally extended from the data line.

Abstract: Provided are a display device and a manufacturing method thereof capable of preventing aggregation of an alignment layer and maintaining uniformly a cell-gap. The display device according to an exemplary embodiment of the invention includes: a substrate including a plurality of pixel areas; a thin film transistor formed on the substrate; a pixel electrode connected to the thin film transistor and formed in the pixel area; a barrier layer formed on the pixel electrode; a roof layer formed on the barrier layer to be spaced apart from the barrier layer with a microcavity therebetween; and a liquid crystal formed to fill the microcavity.

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.

Abstract: Provided is an array substrate including a base substrate, a thin film transistor having a semiconductor layer disposed on a first part of the base substrate. The semiconductor layer includes a source electrode and a drain electrode, a gate electrode disposed on the semiconductor layer and insulated from the semiconductor layer. A light-blocking layer disposed between the base substrate and the thin film transistor. The light-blocking layer comprises a first layer continuously disposed on and around the first part of the base substrate, and a second layer formed on the first part of the base substrate without extending outside of the first part, the second layer being disposed on the first layer.

Abstract: RC delay in gate lines of a wide display is reduced by using a low resistivity conductor in the gate lines and a different conductor for forming corresponding gate electrodes. More specifically, a corresponding display substrate includes a gate line made of a first gate line metal, a data line made of a first data line metal, a pixel transistor and a first connection providing part. The pixel transistor includes a first active pattern formed of polycrystalline silicon (poly-Si) and a first gate electrode formed there above and made of a conductive material different from the first gate line metal. The first connection providing part connects the first gate electrode to the gate line. On the other hand, the source electrode is integrally extended from the data line.

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.