Abstract: A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an intersection region with the first pattern and a non-intersection region.

Abstract: A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an intersection region with the first pattern and a non-intersection region.

Abstract: A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an intersection region with the first pattern and a non-intersection region.

Abstract: A semiconductor device may be provided. The semiconductor device may include conductive patterns surrounding a channel film. The conductive patterns may be stacked and spaced apart from one another. The semiconductor device may include a gate contact plug coupled to one of the conductive patterns. The semiconductor device may include support pillars penetrating the conductive patterns in a periphery of the gate contact plug.

Abstract: A semiconductor device may be provided. The semiconductor device may include conductive patterns surrounding a channel film. The conductive patterns may be stacked and spaced apart from one another. The semiconductor device may include a gate contact plug coupled to one of the conductive patterns. The semiconductor device may include support pillars penetrating the conductive patterns in a periphery of the gate contact plug.

Abstract: A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an intersection region with the first pattern and a non-intersection region.

Abstract: The present disclosure may provide a semiconductor device with an enhanced integration. The device may include a lower pipe gate; an upper pipe gate including a first horizontal portion and first and second protrusions, the first horizontal portion being parallel to the lower pipe gate, the first and second protrusions extending from the first horizontal portion to the lower pipe gate and crossing each other so as to define a pipe channel region; a partition pipe gate disposed between the lower and upper pipe gates, the partition pipe gate dividing the pipe channel region into first and second pipe channel regions; and first and second pipe channel films disposed respectively in the first and second pipe channel regions.

Abstract: The present disclosure may provide a semiconductor device with an enhanced integration. The device may include a lower pipe gate; an upper pipe gate including a first horizontal portion and first and second protrusions, the first horizontal portion being parallel to the lower pipe gate, the first and second protrusions extending from the first horizontal portion to the lower pipe gate and crossing each other so as to define a pipe channel region; a partition pipe gate disposed between the lower and upper pipe gates, the partition pipe gate dividing the pipe channel region into first and second pipe channel regions; and first and second pipe channel films disposed respectively in the first and second pipe channel regions.

Abstract: A method for fabricating an electronic device including a semiconductor memory may include: forming a stack structure in which an interlayer dielectric layer and a material layer are alternately stacked on a substrate; forming a plurality of holes arranged to have a substantially constant interval while exposing the substrate by passing through the stack structure; forming a channel layer in a first hole of the plurality of holes; forming a dummy layer in a second hole of the plurality of holes; forming a mask pattern on a resultant structure including the dummy layer and the channel layer to expose an area extending in a first direction while overlapping the dummy layer arranged in the first direction; and forming a slit by etching the stack structure using the mask pattern as an etching barrier and removing the dummy layer.

Abstract: The present disclosure may provide a semiconductor device with an enhanced integration. The device may include a lower pipe gate; an upper pipe gate including a first horizontal portion and first and second protrusions, the first horizontal portion being parallel to the lower pipe gate, the first and second protrusions extending from the first horizontal portion to the lower pipe gate and crossing each other so as to define a pipe channel region; a partition pipe gate disposed between the lower and upper pipe gates, the partition pipe gate dividing the pipe channel region into first and second pipe channel regions; and first and second pipe channel films disposed respectively in the first and second pipe channel regions.

Abstract: The present disclosure may provide a semiconductor device with an enhanced integration. The device may include a lower pipe gate; an upper pipe gate including a first horizontal portion and first and second protrusions, the first horizontal portion being parallel to the lower pipe gate, the first and second protrusions extending from the first horizontal portion to the lower pipe gate and crossing each other so as to define a pipe channel region; a partition pipe gate disposed between the lower and upper pipe gates, the partition pipe gate dividing the pipe channel region into first and second pipe channel regions; and first and second pipe channel films disposed respectively in the first and second pipe channel regions.

Abstract: A method for fabricating an electronic device including a semiconductor memory may include: forming a stack structure in which an interlayer dielectric layer and a material layer are alternately stacked on a substrate; forming a plurality of holes arranged to have a substantially constant interval while exposing the substrate by passing through the stack structure; forming a channel layer in a first hole of the plurality of holes; forming a dummy layer in a second hole of the plurality of holes; forming a mask pattern on a resultant structure including the dummy layer and the channel layer to expose an area extending in a first direction while overlapping the dummy layer arranged in the first direction; and forming a slit by etching the stack structure using the mask pattern as an etching barrier and removing the dummy layer.

Abstract: A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region.

Abstract: A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region.

Abstract: A method of forming a semiconductor device includes forming an interlayer insulating layer over the semiconductor substrate of a cell region, and forming gate structures over the semiconductor substrate of a peripheral region. Reserved bit line regions are formed in the cell region by etching the interlayer insulating layer, and gates are formed by etching the gate structures in the peripheral region. A capping insulating layer and an isolation layer are formed over the reserved bit line regions and the gates, the isolation layer of the cell region is removed, and an etch-back process is performed on the capping insulating layer, and bit lines are formed in the respective reserved bit line regions. Semiconductor device yields can be enhanced because patterns having a fine critical dimension can be formed in peripheral regions with an increased degree of integration.

Abstract: A method for manufacturing a semiconductor device comprises performing an exposing and developing process using an exposure mask including shading patterns and assistant patterns arranged in parallel to the shading patterns to prevent a scum phenomenon generated when a main pattern is formed in a cell region over a semiconductor substrate, thereby improving characteristics, reliability and yield of the semiconductor device. As a result, the method enables high-integration of the semiconductor device.

Abstract: A semiconductor device including a CMP dummy pattern and a method for manufacturing the same are provided. The warpage of a wafer can be prevented by forming the CMP dummy pattern in the same direction and/or at the same angle as a pattern of a cell region. Accordingly, overlay error caused by etching residues is reduced, thereby improving the yield of the semiconductor device.

Abstract: A method for manufacturing a semiconductor device which includes fine patterns having various critical dimensions (CDs) by adjusting a thickness of spacer used as an etching mask in Spacer Patterning Technology (SPT). The method for manufacturing a semiconductor device includes forming spacers at a different level over an etching target layer and etching the etching target layer exposed among the spacers.

Abstract: A method for processing optical proximity correction is disclosed which eliminates a need for repeated implementation of experiments and result in a reducing the processing time as compared to trial and error. Furthermore, the method can realize an optimal insertion of the assist pattern by applying different conditions to specific layers. The method includes determining whether or not to insert an assist pattern around an outermost pattern. A shape of the assist pattern inserted around the outermost pattern is determined. The contrast of the outermost pattern is compared against a contrast of a cell array pattern. The contrast of the outermost pattern is repeated compared with the contrast of the cell array pattern under a defocus state.

Abstract: A method for manufacturing a semiconductor device comprises performing an exposing and developing process using an exposure mask including shading patterns and assistant patterns arranged in parallel to the shading patterns to prevent a scum phenomenon generated when a main pattern is formed in a cell region over a semiconductor substrate, thereby improving characteristics, reliability and yield of the semiconductor device. As a result, the method enables high-integration of the semiconductor device.