Abstract: Disclosed is tonovel cyclic derivatives having potent inhibiting effect on melanin formation and skin hyper-pigmentation activity with no adverse response to skin. They can be used as the therapeutics for treating and preventing the skin disease caused by over-reproduced melanin.

Abstract: In one aspect a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

Abstract: The present invention relates to a modified CpG oligodeoxynucleotide (ODN) which is prepared by coupling a consecutive sequence of deoxyribothymine (dT) to the 3?-terminus of CpG ODN having immunoregularory function, thereby improving immunoactivity of splenocytes, macrophages and peripheral mononuclear cells, and therefore, can be effectively used as a vaccine adjuvant for preventing and treating hepatitis B or an anticancer agent. Since the phosphorothioate CpG ODN having the consecutive sequence of dT at its 3?-terminus shows high activity inducing Th-1 immune response and does not elicit in vivo toxicity with guaranteeing its safety, it can be effectively used as a vaccine adjuvant.

Abstract: According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line.

Abstract: According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line.

Abstract: The present invention relates to a modified CpG oligodeoxynucleotide (ODN) which is prepared by coupling a consecutive sequence of deoxyribothymine (dT) to the 3?-terminus of CpG ODN having immunoregularory function, thereby improving immunoactivity of splenocytes, macrophages and peripheral mononuclear cells, and therefore, can be effectively used as a vaccine adjuvant for preventing and treating hepatitis B or an anti-cancer agent. Since the phosphorothioate CpG ODN having the consecutive sequence of dT at its 3?-terminus shows high activity inducing Th-1 immune response and does not elicit in vivo toxicity with guaranteeing its safety, it can be effectively used as a vaccine adjuvant.

Abstract: In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

Abstract: According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line.

Abstract: According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line.

Abstract: Memory devices include a memory cell array, a column selection circuit electrically coupled to the memory cell array and a data line driver circuit. The data line driver circuit is configured to drive an output port of the memory device with read data received from the column selection circuit during a read cycle time interval. The data line driver circuit is further configured to support an extended read cycle time interval by switching from a non-latching mode of operation during a leading portion of the read cycle time interval to a latching mode of operation during a trailing portion of the read cycle time interval. The data line driver circuit may include a drive inverter having an output electrically connected to one of a plurality of output pins associated with an output port and a feedback inverter having an input electrically connected to the output of the drive inverter.

Abstract: According to some embodiments, a nonvolatile semiconductor memory device includes high voltage circuits that prevent high voltages, which are applied to bitlines during an erase operation, from being applied to low voltage circuits that are operable with low voltages. Each high voltage circuit includes a first switching circuit for selectively isolating the low voltage circuit from the bitlines, and a second switching circuit for inhibiting a leakage current to the low voltage circuit from the bitlines. The second switching circuit is connected between the first switching circuit and the low voltage circuit.

Abstract: A carrier moving system for a painting process of a vehicle includes a loaded section, an unloaded section, and a plurality of multi-joint type carriers. The multi-joint carriers include a driving part and a driven part. A guiding monorail is disposed through both the loaded section and the unloaded section so as to guide each multi-joint type carrier through both sections. A storing monorail disposed in the unloaded section and arranged in parallel with the guiding monorail and a switching unit for switching a position of the driven part of the multi-joint type carrier between the guiding monorail and the storing monorail.

Abstract: Memory devices include a memory cell array, a column selection circuit electrically coupled to the memory cell array and a data line driver circuit. The data line driver circuit is configured to drive an output port of the memory device with read data received from the column selection circuit during a read cycle time interval. The data line driver circuit is further configured to support an extended read cycle time interval by switching from a non-latching mode of operation during a leading portion of the read cycle time interval to a latching mode of operation during a trailing portion of the read cycle time interval. The data line driver circuit may include a drive inverter having an output electrically connected to one of a plurality of output pins associated with an output port and a feedback inverter having an input electrically connected to the output of the drive inverter.

Abstract: According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line.

Abstract: In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

Abstract: A carrier moving system for a painting process of a vehicle includes a loaded section, an unloaded section, and a plurality of multi-joint type carriers. The multi-joint carriers include a driving part and a driven part. A guiding monorail is disposed through both the loaded section and the unloaded section so as to guide each multi-joint type carrier through both sections. A storing monorail disposed in the unloaded section and arranged in parallel with the guiding monorail and a switching unit for switching a position of the driven part of the multi-joint type carrier between the guiding monorail and the storing monorail.

Abstract: According to some embodiments, a nonvolatile semiconductor memory device includes high voltage circuits that prevent high voltages, which are applied to bitlines during an erase operation, from being applied to low voltage circuits that are operable with low voltages. Each high voltage circuit includes a first switching circuit for selectively isolating the low voltage circuit from the bitlines, and a second switching circuit for inhibiting a leakage current to the low voltage circuit from the bitlines. The second switching circuit is connected between the first switching circuit and the low voltage circuit.