Abstract: An atomic layer deposition method for manufacturing a platinum-based alloy catalyst includes applying a support in a reactor and depositing an alloy of platinum and a non-platinum metal on the support through a super cycle comprising a first sub-cycle and a second sub-cycle.

Abstract: A deep learning-based MLCC stacked alignment inspection system includes an integrated defect detection unit configured to detect core areas requiring inspection of image data in which a stacked structure is photographed from a semiconductor MLCC chip by using at least one deep learning-based core area detection model, perform segmentation in the detected core areas, determine whether a defect exists according to a standard margin percentage range, and enable defect detection by generating normal and/or defective data based on the determination result, a result analysis unit configured to perform visualization for respective results of the core area detection, segmentation, and defect detection of the integrated defect detection unit, and provide stepwise analysis data for the visualized respective results so as to determine whether to modify corresponding data, and a data storage configured to store the normal and/or defective data, and stepwise analysis data.

Abstract: Provided are a GPU and a method of managing a memory address thereby. TLBs are configured using an SRAM and an STT-MRAM so that a storage capacity is significantly improved compared to a case where a TLB is configured using an SRAM. Accordingly, the page hit rate of a TLB can be increased, thereby improving the throughput of a device. Furthermore, after a PTE is first written in the SRAM, a PTE having high frequency of use is selected and moved to the STT-MRAM. Accordingly, an increase in TLB update time which may occur due to the use of the STT-MRAM having a low write speed can be prevented. Furthermore, a read time and read energy consumption can be reduced.

Abstract: Provided are a GPU and a method of managing a memory address thereby. TLBs are configured using an SRAM and an STT-MRAM so that a storage capacity is significantly improved compared to a case where a TLB is configured using an SRAM. Accordingly, the page hit rate of a TLB can be increased, thereby improving the throughput of a device. Furthermore, after a PTE is first written in the SRAM, a PTE having high frequency of use is selected and moved to the STT-MRAM. Accordingly, an increase in TLB update time which may occur due to the use of the STT-MRAM having a low write speed can be prevented. Furthermore, a read time and read energy consumption can be reduced.