Abstract: A barristor-based photodetector is disclosed. The photodetector according to an embodiment comprises: a substrate; a gate electrode which is laminated on the substrate; a first electrode and a second electrode which are laminated on the substrate and spaced apart from the gate electrode; a graphene layer which is formed between the substrate and the second electrode and extends toward the first electrode; and a gate insulating layer which is formed between the gate electrode and the graphene layer.

Abstract: A barristor-based photodetector is disclosed. The photodetector according to an embodiment comprises: a substrate; a gate electrode which is laminated on the substrate; a first electrode and a second electrode which are laminated on the substrate and spaced apart from the gate electrode; a graphene layer which is formed between the substrate and the second electrode and extends toward the first electrode; and a gate insulating layer which is formed between the gate electrode and the graphene layer.

Abstract: A barristor-based photodetector is disclosed. The photodetector according to an embodiment comprises: a substrate; a gate electrode which is laminated on the substrate; a first electrode and a second electrode which are laminated on the substrate and spaced apart from the gate electrode; a graphene layer which is formed between the substrate and the second electrode and extends toward the first electrode; and a gate insulating layer which is formed between the gate electrode and the graphene layer.

Abstract: Disclosed are a two-dimensional semiconductor in which an energy band gap changes with thickness, a manufacturing method therefor, and a semiconductor device comprising the same. A two-dimensional semiconductor according to an embodiment comprises: a first layer having a first thickness; and a second layer having a second thickness, wherein the first thickness and the second thickness are different from each other, the first layer forms a first junction with a first electrode, and the second layer forms a second junction with a second electrode.

Abstract: Disclosed are a two-dimensional semiconductor in which an energy band gap changes with thickness, a manufacturing method therefor, and a semiconductor device comprising the same. A two-dimensional semiconductor according to an embodiment comprises: a first layer having a first thickness; and a second layer having a second thickness, wherein the first thickness and the second thickness are different from each other, the first layer forms a first junction with a first electrode, and the second layer forms a second junction with a second electrode.

Abstract: A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.

Abstract: A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor.

Abstract: Methods of fabricating graphene using an alloy catalyst may include forming an alloy catalyst layer including nickel on a substrate and forming a graphene layer by supplying hydrocarbon gas onto the alloy catalyst layer. The alloy catalyst layer may include nickel and at least one selected from the group consisting of copper, platinum, iron and gold. When the graphene is fabricated, a catalyst metal that reduces solubility of carbon in Ni may be used together with Ni in the alloy catalyst layer. An amount of carbon that is dissolved may be adjusted and a uniform graphene monolayer may be fabricated.

Abstract: According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 1019 cm?3, and a depletion width of less than or equal to 3 nm.

Abstract: A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate.

Abstract: A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element.

Abstract: A switching device includes a semiconductor layer, a graphene layer, a gate insulation layer, and a gate formed in a three-dimensional stacking structure between a first electrode and a second electrode formed on a substrate.

Abstract: A graphene electronic device includes a graphene channel layer on a substrate, a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer, a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, and a gate electrode on the gate oxide. The gate oxide has substantially the same shape as the graphene channel layer between the source electrode and the drain electrode.

Abstract: A method of transferring graphene includes patterning an upper surface of a substrate to form at least one trench therein, providing a graphene layer on the substrate, the graphene layer including an adhesive liquid thereon, pressing the graphene layer with respect to the substrate, and removing the adhesive liquid by drying the substrate.

Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.

Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Abstract: Inverter logic devices include a gate oxide on a back substrate, a first graphene layer and a second graphene layer separated from each other on the gate oxide, a first electrode layer and a first semiconductor layer separated from each other on the first graphene layer, a second electrode layer and a second semiconductor layer separated from each other on the second graphene layer, and an output electrode on the first and second semiconductor layers and configured to output an output signal. The first semiconductor layer is doped with a different type of impurities selected from n-type impurities and p-type impurities than the second semiconductor layer.

Abstract: Example embodiments relate to methods of manufacturing and transferring a larger-sized graphene layer. A method of transferring a larger-sized graphene layer may include forming a graphene layer, a protection layer, and an adhesive layer on a substrate and removing the substrate. The graphene layer may be disposed on a transferring substrate by sliding the graphene layer onto the transferring substrate.

Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.

Abstract: According to example embodiments, a tunneling field-effect transistor (TFET) includes a first electrode on a substrate, a semiconductor layer on a portion of the first electrode, a graphene channel on the semiconductor layer, a second electrode on the graphene channel, a gate insulating layer on the graphene channel, and a gate electrode on the gate insulating layer. The first electrode may include a portion that is adjacent to the first area of the substrate. The semiconductor layer may be between the graphene channel and the portion of the first electrode. The graphene channel may extend beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate.