Patents by Inventor Hyun-Seung Song
Hyun-Seung Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978775Abstract: A semiconductor device comprising a gate electrode on a substrate, a source/drain pattern on the substrate on a side of the gate electrode, and a gate contact plug on the gate electrode are disclosed. The gate contact plug may include a first gate contact segment, and a second gate contact segment that extends in a vertical direction from a top surface of the first gate contact segment. An upper width of the first gate contact segment may be greater than a lower width of the second gate contact segment.Type: GrantFiled: June 16, 2022Date of Patent: May 7, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Doohyun Lee, Hyun-Seung Song, Yeongchang Roh, Heonjong Shin, Sora You, Yongsik Jeong
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Patent number: 11961806Abstract: A semiconductor device may include a substrate including a first region and a second region and a first active pattern on the first region. The first active pattern may include a pair of first source/drain patterns and a first channel pattern therebetween, and the first channel pattern may include a plurality of first semiconductor patterns stacked on the substrate. The semiconductor device may further include a first gate electrode, which is provided on the first channel patterns, and a supporting pattern, which is provided on side surfaces of the plurality of first semiconductor patterns to connect the side surfaces of the plurality of first semiconductor patterns to each other.Type: GrantFiled: June 21, 2021Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Noh Yeong Park, Beomjin Park, Dong Il Bae, Sangwon Baek, Hyun-Seung Song
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Publication number: 20240100969Abstract: An embodiment structural battery for an electric vehicle includes an upper rail and a lower rail coupled with the upper rail, wherein the upper rail and the lower rail are electrically connected with each other by a terminal and a wiring, so that the upper rail and the lower rail electrically connected with each other serve as both the structural battery and a roof rail of a vehicle body.Type: ApplicationFiled: September 22, 2023Publication date: March 28, 2024Inventors: Won Ki Song, Chun-Gon Kim, Hyun Wook Park, Joo-Seung Choi, Jung-Eon Noh
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Publication number: 20240106055Abstract: An embodiment structural battery for an electric vehicle includes a plurality of cells stacked on each other, each of the plurality of cells including a positive electrode layer, an electrolyte layer, and a negative electrode layer stacked with the electrolyte layer between the positive and negative electrodes, wherein the plurality of cells define a battery by electrical connection of a positive electrode terminal and a negative electrode terminal respectively provided in the plurality of cells, structure reinforcement layers stacked on each of an outermost upper layer and an outermost lower layer of the plurality of cells, and carbon fiber current collecting layers stacked between each of the structure reinforcement layers and the plurality of cells.Type: ApplicationFiled: June 19, 2023Publication date: March 28, 2024Inventors: Won Ki Song, Jai Hak Kim, Chun-Gon Kim, Hyun Wook Park, Joo-Seung Choi, Jung-Eon Noh
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Patent number: 11923298Abstract: A semiconductor device includes a first active pattern on a substrate; a first gate electrode crossing the first active pattern; source/drain patterns in an upper portion of the first active pattern and at opposite sides, respectively, of the first gate electrode; a first gate capping pattern on the first gate electrode; an interlayer insulating layer on the source/drain patterns; first and second active contacts penetrating the interlayer insulating layer and being respectively connected to the pair of source/drain patterns; and a first interconnection layer on the first and second active contacts. The first interconnection layer may include a first insulating structure covering a top surface of the second active contact; and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate capping pattern between the first and second active contacts.Type: GrantFiled: June 2, 2022Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Seung Song, Kwang-Young Lee, Jonghyun Lee
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Publication number: 20230053251Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.Type: ApplicationFiled: October 31, 2022Publication date: February 16, 2023Inventors: Seung Seok HA, Hyun Seung SONG, Hyo Jin KIM, Kyoung Mi PARK, Guk Il AN
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Publication number: 20230011401Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.Type: ApplicationFiled: September 16, 2022Publication date: January 12, 2023Inventors: Hyun-Seung Song, Tae-Yeol Kim, Jae-Jik Baek
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Patent number: 11488953Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.Type: GrantFiled: September 29, 2020Date of Patent: November 1, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Seok Ha, Hyun Seung Song, Hyo Jin Kim, Kyoung Mi Park, Guk Il An
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Patent number: 11482602Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.Type: GrantFiled: September 28, 2020Date of Patent: October 25, 2022Inventors: Hyun-Seung Song, Tae-Yeol Kim, Jae-Jik Baek
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Publication number: 20220336661Abstract: A semiconductor device includes a first impurity region on a substrate; a channel pattern protruding from an upper surface of the substrate, the channel pattern extending in a first direction substantially parallel to the upper surface of the substrate; a second impurity region on the channel pattern, the second impurity region covering an entire upper surface of the channel pattern; a gate structure on a sidewall of the channel pattern and the substrate adjacent to the channel pattern; a first contact pattern on the second impurity region; a second contact pattern that is electrically connected to the gate structure; and a spacer between the first contact pattern and the second contact pattern. The spacer completely surrounds the second contact pattern in plan view, and the first contact pattern partially surrounds the second contact pattern in plan view.Type: ApplicationFiled: July 5, 2022Publication date: October 20, 2022Applicant: SAMSUNG ELECTRONICS CO., LTDInventors: Hyun-Seung SONG, Hyo-Jin KIM, Kyoung-Mi PARK, Hwi-Chan JUN, SeungSeok HA
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Publication number: 20220310809Abstract: A semiconductor device comprising a gate electrode on a substrate, a source/drain pattern on the substrate on a side of the gate electrode, and a gate contact plug on the gate electrode are disclosed. The gate contact plug may include a first gate contact segment, and a second gate contact segment that extends in a vertical direction from a top surface of the first gate contact segment. An upper width of the first gate contact segment may be greater than a lower width of the second gate contact segment.Type: ApplicationFiled: June 16, 2022Publication date: September 29, 2022Inventors: Doohyun Lee, HYUN-SEUNG SONG, YEONGCHANG ROH, HEONJONG SHIN, SORA YOU, YONGSIK JEONG
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Publication number: 20220302017Abstract: A semiconductor device includes a first active pattern on a substrate; a first gate electrode crossing the first active pattern; source/drain patterns in an upper portion of the first active pattern and at opposite sides, respectively, of the first gate electrode; a first gate capping pattern on the first gate electrode; an interlayer insulating layer on the source/drain patterns; first and second active contacts penetrating the interlayer insulating layer and being respectively connected to the pair of source/drain patterns; and a first interconnection layer on the first and second active contacts. The first interconnection layer may include a first insulating structure covering a top surface of the second active contact; and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate capping pattern between the first and second active contacts.Type: ApplicationFiled: June 2, 2022Publication date: September 22, 2022Inventors: Hyun-Seung SONG, Kwang-Young LEE, Jonghyun LEE
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Patent number: 11393909Abstract: A semiconductor device comprising a gate electrode on a substrate, a source/drain pattern on the substrate on a side of the gate electrode, and a gate contact plug on the gate electrode are disclosed. The gate contact plug may include a first gate contact segment, and a second gate contact segment that extends in a vertical direction from a top surface of the first gate contact segment. An upper width of the first gate contact segment may be greater than a lower width of the second gate contact segment.Type: GrantFiled: July 17, 2019Date of Patent: July 19, 2022Inventors: Doohyun Lee, Hyun-Seung Song, Yeongchang Roh, Heonjong Shin, Sora You, Yongsik Jeong
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Patent number: 11380791Abstract: A semiconductor device includes a first impurity region, a channel pattern, a second impurity region, a gate structure, a first contact pattern, a second contact pattern and a spacer. The first impurity region may be formed on a substrate. The channel pattern may protrude from an upper surface of the substrate. The second impurity region may be formed on the channel pattern. The gate structure may be formed on a sidewall of the channel pattern and the substrate adjacent to the channel pattern, and the gate structure may include a gate insulation pattern and a gate electrode. The first contact pattern may contact an upper surface of the second impurity region. The second contact pattern may contact a surface of the gate electrode. The spacer may be formed between the first and second contact patterns. The spacer may surround a portion of a sidewall of the second contact pattern, and the spacer may contact a sidewall of each of the first and second contact patterns.Type: GrantFiled: December 19, 2018Date of Patent: July 5, 2022Assignee: SAMSUNG ELECTRONICS CO.. LTD.Inventors: Hyun-Seung Song, Hyo-Jin Kim, Kyoung-Mi Park, Hwi-Chan Jun, Seung-Seok Ha
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Publication number: 20220199798Abstract: A semiconductor device includes a substrate that includes a peripheral region, a first active pattern on the peripheral region, a first source/drain pattern on the first active pattern, a first channel pattern formed on the first active pattern and connected to the first source/drain pattern, wherein the first channel pattern includes semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode that extends in a first direction and crosses the first channel pattern, a gate insulating layer interposed between the first gate electrode and the first channel pattern, a first gate contact disposed on the first gate electrode and that extends in the first direction, and a first dielectric layer interposed between the first gate electrode and the first gate contact. The first dielectric layer is interposed between the first gate contact and the first gate electrode and extends in the first direction.Type: ApplicationFiled: December 5, 2021Publication date: June 23, 2022Inventors: Myung Gil Kang, Keun Hwi Cho, Sangdeok Kwon, Dongwon Kim, Hyun-Seung Song
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Patent number: 11355434Abstract: A semiconductor device includes a first active pattern on a substrate; a first gate electrode crossing the first active pattern; source/drain patterns in an upper portion of the first active pattern and at opposite sides, respectively, of the first gate electrode; a first gate capping pattern on the first gate electrode; an interlayer insulating layer on the source/drain patterns; first and second active contacts penetrating the interlayer insulating layer and being respectively connected to the pair of source/drain patterns; and a first interconnection layer on the first and second active contacts. The first interconnection layer may include a first insulating structure covering a top surface of the second active contact; and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate capping pattern between the first and second active contacts.Type: GrantFiled: September 10, 2020Date of Patent: June 7, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Seung Song, Kwang-Young Lee, Jonghyun Lee
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Publication number: 20220173053Abstract: A semiconductor device may include a substrate including a first region and a second region and a first active pattern on the first region. The first active pattern may include a pair of first source/drain patterns and a first channel pattern therebetween, and the first channel pattern may include a plurality of first semiconductor patterns stacked on the substrate. The semiconductor device may further include a first gate electrode, which is provided on the first channel patterns, and a supporting pattern, which is provided on side surfaces of the plurality of first semiconductor patterns to connect the side surfaces of the plurality of first semiconductor patterns to each other.Type: ApplicationFiled: June 21, 2021Publication date: June 2, 2022Inventors: NOH YEONG PARK, BEOMJIN PARK, DONG IL BAE, Sangwon BAEK, HYUN-SEUNG SONG
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Publication number: 20210272893Abstract: A semiconductor device includes a first active pattern on a substrate; a first gate electrode crossing the first active pattern; source/drain patterns in an upper portion of the first active pattern and at opposite sides, respectively, of the first gate electrode; a first gate capping pattern on the first gate electrode; an interlayer insulating layer on the source/drain patterns; first and second active contacts penetrating the interlayer insulating layer and being respectively connected to the pair of source/drain patterns; and a first interconnection layer on the first and second active contacts. The first interconnection layer may include a first insulating structure covering a top surface of the second active contact; and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate capping pattern between the first and second active contacts.Type: ApplicationFiled: September 10, 2020Publication date: September 2, 2021Inventors: Hyun-Seung SONG, Kwang-Young LEE, Jonghyun LEE
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Publication number: 20210217861Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.Type: ApplicationFiled: September 28, 2020Publication date: July 15, 2021Inventors: HYUN-SEUNG SONG, Tae-Yeol Kim, Jae-Jik Baek
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Patent number: 10916534Abstract: A semiconductor device includes a first fin pattern and a second fin pattern in a NMOS region, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench. First and second isolation layers are disposed in the first and second trenches, respectively. A first gate electrode extends lengthwise along a second direction transverse to the first direction and crosses the first fin pattern. A second gate electrode extends lengthwise along the second direction and crosses the second fin pattern. Spaced apart third and fourth gate electrodes extend lengthwise along the second direction on the second isolation layer.Type: GrantFiled: April 26, 2019Date of Patent: February 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Seok Ha, Kyoung-Mi Park, Hyun-Seung Song, Keon Yong Cheon, Dae Won Ha