Abstract: A display driving device includes a timing controller configured to generate test data having a predetermined periodicity, and a source driver configured to drive source lines of a display panel using the test data, determine that a bit error has been generated when aperiodicity appears in the test data, and measure a bit error rate (BER) based on the bit error.

Abstract: A data receiver includes a plurality of samplers, each of the samplers amplifies a difference between a first reference voltage and an input voltage and amplifies a difference between a second reference voltage and the input voltage. Operational paths of the samplers are differently controlled according to a level of second data corresponding to the second reference voltage, and first data corresponding to the first reference voltage is past data preceding current data and the second data is past data preceding the first data in the sampler.

Abstract: A display device includes a data generator configured to generate a clock-embedded data packet, and a controller configured to control operation of the data generator. The data packet comprises a header, a first symbol comprising address information therein, and a second symbol not comprising address information, and the header comprises address information of the first symbol.

Abstract: A method of operating a source driver, a display driving circuit, and a method of operating the display driving circuit are provided. The method of operating the source driver including a receiver, includes determining a parameter value of the receiver for optimizing a receiving of the receiver, through training, and transmitting the parameter value to a timing controller external to the source driver. The method of operating the source driver further includes, based on an abnormal state occurring in the receiving of the receiver, receiving the transmitted parameter value from the timing controller, and optimizing the receiving of the receiver based on the received parameter value.

Abstract: A method of operating a receiver includes a controller of the receiver determining whether a full initialization or a partial initialization of the receiver is needed; the controller adjusting alternating current (AC) characteristics and direct current (DC) characteristics of the receiver in a full initialization mode, and the controller adjusting the DC characteristics of the receiver in a partial initialization mode when the controller determines the partial initialization is needed.

Abstract: A data receiver includes a plurality of samplers, each of the samplers amplifies a difference between a first reference voltage and an input voltage and amplifies a difference between a second reference voltage and the input voltage. Operational paths of the samplers are differently controlled according to a level of second data corresponding to the second reference voltage, and first data corresponding to the first reference voltage is past data preceding current data and the second data is past data preceding the first data in the sampler.

Abstract: A display driving circuit includes a clock dividing unit and a data processing unit. The clock dividing unit receives a first clock signal, generates a second clock signal having a second clock frequency by dividing the first clock signal having a first clock frequency, and outputs the second clock signal. The data processing unit receive the first clock signal, the second clock signal, and input data with a first data frequency, separates input data into first data and second data, outputs the first data based on the second clock signal, and outputs the second data with a second data frequency based on the first clock signal.

Abstract: A read circuit of a disk drive system that adaptively reduces signal-dependent noise including a sequence detector, a signal-dependent adaptive engine and a signal-dependent post-processor. The sequence detector recovers a data sequence from equalized data. The signal-dependent adaptive engine generates signal-dependent coefficients, a mean value and a standard deviation of a signal-dependent error. The signal-dependent post-processor corrects the signal-dependent error.

Abstract: There is provided an apparatus and method for initializing a tap coefficient of an adaptive equalizer constituting a read path for a storage medium, where the apparatus includes an FIR filter, a Viterbi decoder, a level error detector, and a tap coefficient updater, the FIR filter receives a first signal stream and outputs the first signal stream in the form of a second signal stream, the Viterbi decoder corrects a bit error of the second signal stream, the level error detector detects a level error between the second signal stream and a third signal stream that is an ideal output signal corresponding to the second signal stream, the tap coefficient updater selects a tap coefficient minimizing the level error and provides the selected tap coefficient as a tap coefficient of the FIR filter, the tap coefficient minimizing the level error is determined as an initial value in a system initialization mode, and the determined initial value is used as an initial value of the tap coefficient of the FIR filter in a no

Abstract: A read circuit of a disk drive system that adaptively reduces signal-dependent noise including a sequence detector, a signal-dependent adaptive engine and a signal-dependent post-processor. The sequence detector recovers a data sequence from equalized data. The signal-dependent adaptive engine generates signal-dependent coefficients, a mean value and a standard deviation of a signal-dependent error. The signal-dependent post-processor corrects the signal-dependent error.

Abstract: There is provided an apparatus and method for initializing a tap coefficient of an adaptive equalizer constituting a read path for a storage medium, where the apparatus includes an FIR filter, a Viterbi decoder, a level error detector, and a tap coefficient updater, the FIR filter receives a first signal stream and outputs the first signal stream in the form of a second signal stream, the Viterbi decoder corrects a bit error of the second signal stream, the level error detector detects a level error between the second signal stream and a third signal stream that is an ideal output signal corresponding to the second signal stream, the tap coefficient updater selects a tap coefficient minimizing the level error and provides the selected tap coefficient as a tap coefficient of the FIR filter, the tap coefficient minimizing the level error is determined as an initial value in a system initialization mode, and the determined initial value is used as an initial value of the tap coefficient of the FIR filter in a no

Abstract: A memory device includes first and second power supply pads configured to be connected to a power supply. The memory device further includes a data output circuit that receives power via the first power supply pad and outputs data responsive to an internal clock signal, and a delay-locked loop (DLL) circuit that receives power via the second power supply pad independently of the first power supply pad and that generates the internal clock signal responsive to an external clock signal.

Abstract: An apparatus and method of controlling gain in a channel signal. The apparatus may include a gain compensating section that compensates a first gain therein based on the channel signal and a first gain control signal. The apparatus may include an equalizer for generating a gain signal based on the first compensating signal, the gain signal representing a second gain therein; and a gain compensating controller for generating, based on the gain signal, the first gain control signal for compensating the first gain.

Abstract: Data can be buffered for an integrated circuit memory device by converting a plurality of serial data bits into a parallel format such that even ones of the plurality of serial data bits are provided at a first conversion output node and odd ones of the plurality of serial data bits are provided at a second conversion output node wherein a first odd data bit, a first even data bit, a second odd data bit, and a second even data bit comprise four consecutive data bits of the plurality of serial data bits. The first even and odd data bits from the first and second conversion output nodes are provided at first and second latch output nodes during a first period of time, and the second even and odd data bits from the first and second conversion output nodes are provided at third and fourth latch output nodes during a second period of time wherein the first and second periods of time are non-overlapping.

Abstract: Data can be buffered for an integrated circuit memory device by converting a plurality of serial data bits into a parallel format such that even ones of the plurality of serial data bits are provided at a first conversion output node and odd ones of the plurality of serial data bits are provided at a second conversion output node wherein a first odd data bit, a first even data bit, a second odd data bit, and a second even data bit comprise four consecutive data bits of the plurality of serial data bits. The first even and odd data bits from the first and second conversion output nodes are provided at first and second latch output nodes during a first period of time, and the second even and odd data bits from the first and second conversion output nodes are provided at third and fourth latch output nodes during a second period of time wherein the first and second periods of time are non-overlapping.

Abstract: A memory device includes first and second power supply pads configured to be connected to a power supply. The memory device further includes a data output circuit that receives power via the first power supply pad and outputs data responsive to an internal clock signal, and a delay-locked loop (DLL) circuit that receives power via the second power supply pad independently of the first power supply pad and that generates the internal clock signal responsive to an external clock signal.

Abstract: A semiconductor memory device for implementing high speed operation of a delay locked loop (DLL) generates internal clock signals synchronized with external clock signals. The semiconductor memory device includes a first input clock buffer for receiving a pair of external clock signals to generate a reference clock signal and a DLL which receives the reference clock signal and a feedback reference clock signal. The respective phases of the reference clock signal and the feedback reference clock signal are compared, and a pair of internal clock signals are generated. The semiconductor memory device further includes a first feedback clock buffer which receives the pair of internal signals and generates a first feedback clock signal; a second feedback clock buffer which receives the pair of internal signals and generates a second feedback clock signal, and a second input clock buffer which receives the first and second feedback clock signals and generates the feedback reference clock signal.

Abstract: A semiconductor memory device for implementing high speed operation of a delay locked loop (DLL) generates internal clock signals synchronized with external clock signals. The semiconductor memory device includes a first input clock buffer for receiving a pair of external clock signals to generate a reference clock signal and a DLL which receives the reference clock signal and a feedback reference clock signal. The respective phases of the reference clock signal and the feedback reference clock signal are compared, and a pair of internal clock signals are generated. The semiconductor memory device further includes a first feedback clock buffer which receives the pair of internal signals and generates a first feedback clock signal, a second feedback clock buffer which receives the pair of internal signals and generates a second feedback clock signal, and a second input clock buffer which receives the first and second feedback clock signals and generates the feedback reference clock signal.