Patents by Inventor Hyung Gil Baik

Hyung Gil Baik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7115442
    Abstract: Disclosed is a ball grid array package with stacked center pad chips, which realizes a BGA package with stacked chips using center pad type semiconductor chips, and a method for manufacturing the same. The semiconductor chips are glued on each of upper and lower circuit boards, which have active surfaces facing each other; the chip pads are connected to each of the upper and lower circuit boards with gold wires; the upper and lower circuit boards are joined together with bumps interposed between them for electrical connection; the upper circuit board is included in a package mold; and the opposite ends of the lower circuit board are exposed to the lower portion of the package mold. The lower circuit board can be made of flexible insulation film. The exposed opposite ends of the lower circuit board can have solder balls formed thereon. Also, the opposite ends of the lower circuit board may be joined to a printed circuit board. Solder balls may be formed on the lower surface of the printed circuit board.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: October 3, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyung Gil Baik, Ki Ill Moon
  • Patent number: 6841863
    Abstract: Disclosed is a ball grid array package with stacked center pad chips, which realizes a BGA package with stacked chips using center pad type semiconductor chips, and a method for manufacturing the same. The semiconductor chips are glued on each of upper and lower circuit boards, which have active surfaces facing each other; the chip pads are connected to each of the upper and lower circuit boards with gold wires; the upper and lower circuit boards are joined together with bumps interposed between them for electrical connection; the upper circuit board is included in a package mold; and the opposite ends of the lower circuit board are exposed to the lower portion of the package mold. The lower circuit board can be made of flexible insulation film. The exposed opposite ends of the lower circuit board can have solder balls formed thereon. Also, the opposite ends of the lower circuit board may be joined to a printed circuit board. Solder balls may be formed on the lower surface of the printed circuit board.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: January 11, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyung Gil Baik, Ki Ill Moon
  • Publication number: 20040256443
    Abstract: Disclosed is a ball grid array package with stacked center pad chips, which realizes a BGA package with stacked chips using center pad type semiconductor chips, and a method for manufacturing the same. The semiconductor chips are glued on each of upper and lower circuit boards, which have active surfaces facing each other; the chip pads are connected to each of the upper and lower circuit boards with gold wires; the upper and lower circuit boards are joined together with bumps interposed between them for electrical connection; the upper circuit board is included in a package mold; and the opposite ends of the lower circuit board are exposed to the lower portion of the package mold. The lower circuit board can be made of flexible insulation film. The exposed opposite ends of the lower circuit board can have solder balls formed thereon. Also, the opposite ends of the lower circuit board may be joined to a printed circuit board. Solder balls may be formed on the lower surface of the printed circuit board.
    Type: Application
    Filed: July 15, 2004
    Publication date: December 23, 2004
    Inventors: Hyung Gil Baik, Ki Ill Moon
  • Patent number: 6677181
    Abstract: The stack package includes at least two semiconductor chips disposed up and down. Bonding pads are formed in the respective semiconductor chips along a center line. Inner leads of a first lead frame and a second lead frame are attached to bonding-pad-disposed faces of the respective semiconductor chips. The inner lead of each lead frame is electrically connected to its corresponding bonding pad by means of metal wires. The inner lead of the first lead frame is also electrically connected to the second lead frame by utilizing a conductive adhesive material. A connecting hole is formed in the outer end of the inner lead for better electrical connection when soldered. The entire resultant structure is molded with an epoxy compound so as to expose a connecting part between the first and second lead frames and an outer lead of the second lead frame.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: January 13, 2004
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Myung Geun Park, Chang Jun Park, Nam Soo Lee, Hyung Gil Baik, Yoon Hwa Choi
  • Publication number: 20030205801
    Abstract: Disclosed is a ball grid array package with stacked center pad chips, which realizes a BGA package with stacked chips using center pad type semiconductor chips, and a method for manufacturing the same. The semiconductor chips are glued on each of upper and lower circuit boards, which have active surfaces facing each other; the chip pads are connected to each of the upper and lower circuit boards with gold wires; the upper and lower circuit boards are joined together with bumps interposed between them for electrical connection; the upper circuit board is included in a package mold; and the opposite ends of the lower circuit board are exposed to the lower portion of the package mold. The lower circuit board can be made of flexible insulation film. The exposed opposite ends of the lower circuit board can have solder balls formed thereon. Also, the opposite ends of the lower circuit board may be joined to a printed circuit board. Solder balls may be formed on the lower surface of the printed circuit board.
    Type: Application
    Filed: December 27, 2002
    Publication date: November 6, 2003
    Inventors: Hyung Gil Baik, Ki Ill Moon
  • Publication number: 20020185743
    Abstract: The present invention relates to a wafer level chip-scale package and a method for manufacturing such a package. The chip-scale package includes a semiconductor chip having chip pads, a conductor formed on the semiconductor chip and connected to a corresponding chip pad ball land on an extended portion of the conductor, an adhesive layer provided between the semiconductor chip and the conductor, a conductive plug filling the opening part connecting the chip pad to the conductor, a molded body covering the conductor and conductive plug while exposing the ball lands, and a substrate onto which the inserted semiconductor chip is mounted conductive structures and provided to electrically connect and affix the semiconductor chip to the substrate.
    Type: Application
    Filed: December 21, 2001
    Publication date: December 12, 2002
    Inventor: Hyung Gil Baik
  • Publication number: 20020005575
    Abstract: The present invention relates to a stack package, as well as a method for fabricating the same, the stack package includes at least two semiconductor chips disposed up and down. Bonding pads are formed in the respective semiconductor chips along a center line. Inner leads of a first lead frame and a second lead frame are attached to bonding pad-disposed faces of the respective semiconductor chips. The inner lead of each lead frame is electrically connected to its corresponding bonding pad by means of metal wires. The inner lead of the first lead frame is also electrically connected to the second lead frame. The entire structure is molded with an epoxy compound so as to expose a connecting part between the first and second lead frames and an outer lead of the second lead frame.
    Type: Application
    Filed: September 10, 2001
    Publication date: January 17, 2002
    Inventors: Myung Geun Park, Chang Jun Park, Nam Soo Lee, Hyung Gil Baik, Yoon Hwa Choi
  • Patent number: 6316825
    Abstract: The present invention relates to a stack package, as well as a method for fabricating the same, the stack package includes at least two semiconductor chips disposed up and down. Bonding pads are formed in the respective semiconductor chips along a center line. Inner leads of a first lead frame and a second lead frame are attached to bonding pad-disposed faces of the respective semiconductor chips. The inner lead of each lead frame is electrically connected to its corresponding bonding pad by means of metal wires. The inner lead of the first lead frame is also electrically connected to the second lead frame. The entire structure is molded with an epoxy compound so as to expose a connecting part between the first and second lead frames and an outer lead of the second lead frame.
    Type: Grant
    Filed: May 10, 1999
    Date of Patent: November 13, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Myung Geun Park, Chang Jun Park, Nam Soo Lee, Hyung Gil Baik, Yoon Hwa Choi