Patents by Inventor Hyung Joo Shin

Hyung Joo Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10249533
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of gate structures spaced apart from each other on a fin, forming an inorganic plug portion on the fin between at least two gate structures of the plurality of gate structures, forming a dielectric layer on the fin and between remaining gate structures of the plurality of gate structures, forming an organic planarizing layer (OPL) on the plurality of gate structures and on the inorganic plug portion, removing a portion of the OPL to expose the inorganic plug portion, selectively removing the inorganic plug portion, and forming a contact on the fin in place of the removed inorganic plug portion.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Shearer, John R. Sporre, Nicole A. Saulnier, Hyung Joo Shin
  • Patent number: 10170323
    Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: January 1, 2019
    Assignee: Lam Research Corporation
    Inventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyung Joo Shin
  • Patent number: 10167558
    Abstract: An approach to optimizing the throughput in an atomic layer deposition process. The approach charges a first wafer chamber with a first gas from a first storage tank for a first cycle run and determines whether the first cycle run has completed. The approach transfers the first gas from the first wafer chamber to a second wafer chamber and charges the first wafer chamber with a second gas from a second storage tank for a second cycle run and determines whether the second cycle run has completed. The approach transfers the first gas from the second wafer chamber to the first storage tank and transfers the second gas from the first wafer chamber to the second wafer chamber for a third cycle run. The approach determines whether the third cycle run has completed and transfers the second gas from the second wafer chamber to the second storage tank.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Fee Li Lie, Siva Kanakasabapathy, Eric Miller, Hyung Joo Shin
  • Publication number: 20170170026
    Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation.
    Type: Application
    Filed: February 23, 2017
    Publication date: June 15, 2017
    Inventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyung Joo Shin
  • Patent number: 9620377
    Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: April 11, 2017
    Assignee: Lab Research Corporation
    Inventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyung Joo Shin
  • Publication number: 20160163558
    Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation.
    Type: Application
    Filed: July 20, 2015
    Publication date: June 9, 2016
    Inventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyung Joo Shin