Patents by Inventor Hyungki Huh
Hyungki Huh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Integrated circuit package having inductance loop formed from same-pin-to-same-bonding-pad structure
Patent number: 7952442Abstract: An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.Type: GrantFiled: November 16, 2005Date of Patent: May 31, 2011Assignee: GCT Semiconductor, Inc.Inventors: Yido Koo, Hyungki Huh, Kang Yoon Lee, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee -
Patent number: 7768097Abstract: An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction.Type: GrantFiled: August 27, 2004Date of Patent: August 3, 2010Assignee: GCT Semiconductor, Inc.Inventors: Yido Koo, Hyungki Huh, Kang Yoon Lee, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee
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Patent number: 7071535Abstract: An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors.Type: GrantFiled: August 27, 2004Date of Patent: July 4, 2006Assignee: GCT Semiconductor, Inc.Inventors: Yido Koo, Hyungki Huh, Kang Yoon Lee, Jeong-Woo Lee, Joonban Park, Kyeongho Lee
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Integrated circuit package having inductance loop formed from same-pin-to-same-bonding-pad structure
Publication number: 20060081973Abstract: An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.Type: ApplicationFiled: November 16, 2005Publication date: April 20, 2006Inventors: Yido Koo, Hyungki Huh, Kang Lee, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee -
Publication number: 20050045988Abstract: An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors.Type: ApplicationFiled: August 27, 2004Publication date: March 3, 2005Inventors: Yido Koo, Hyungki Huh, Kang Yoon Lee, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee
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Integrated circuit package having inductance loop formed from same-pin-to-same-bonding-pad structure
Publication number: 20050045987Abstract: An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.Type: ApplicationFiled: August 27, 2004Publication date: March 3, 2005Inventors: Yido Koo, Hyungki Huh, Kang Lee, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee -
Publication number: 20050045986Abstract: An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction.Type: ApplicationFiled: August 27, 2004Publication date: March 3, 2005Inventors: Yido Koo, Hyungki Huh, Kang Lee, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee
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Patent number: 6704383Abstract: A phase-locked loop (PLL) fractional-N type frequency synthesizer incorporates a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. Further, the synthesizer can incorporate fractional spur compensation circuitry to compensate charge pump ripple whenever a charge pump operates. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes while a control voltage is stably maintained for the voltage controlled oscillator.Type: GrantFiled: August 29, 2001Date of Patent: March 9, 2004Assignee: GCT Semiconductor, Inc.Inventors: Jeongwoo Lee, Yido Koo, Kang Yoon Lee, Eunseok Song, Hyungki Huh, Joonbae Park, Kyeongho Lee
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Patent number: 6553089Abstract: A phase-locked loop (PLL) frequency synthesizer incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider, two phase detectors each using a charge pump stage pumps. A fractional accumulator stage determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes.Type: GrantFiled: August 29, 2001Date of Patent: April 22, 2003Assignee: GCT Semiconductor, Inc.Inventors: Hyungki Huh, Eunseok Song, Kang Yoon Lee, Yido Koo, Jeongwoo Lee, Joonbae Park, Kyeongho Lee
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Publication number: 20020136341Abstract: A phase-locked loop (PLL) frequency synthesizer incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider, two phase detectors each using a charge pump stage pumps. A fractional accumulator stage determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes.Type: ApplicationFiled: August 29, 2001Publication date: September 26, 2002Applicant: GCT Semiconductor, Inc.Inventors: Hyungki Huh, Eunseok Song, Kang Yoon Lee, Yido Koo, Jeongwoo Lee, Joonbae Park
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Publication number: 20020136342Abstract: A phase-locked loop (PLL) fractional-N type frequency synthesizer incorporates a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. Further, the synthesizer can incorporate fractional spur compensation circuitry to compensate charge pump ripple whenever a charge pump operates. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes while a control voltage is stably maintained for the voltage controlled oscillator.Type: ApplicationFiled: August 29, 2001Publication date: September 26, 2002Applicant: GCT Semiconductor, Inc.Inventors: Jeongwoo Lee, Yido Koo, Kang Yoon Lee, Eunseok Song, Hyungki Huh, Joonbae Park