Abstract: A memory string for using in an EEPROM device is provided which has two selection transistors and a plurality of depletion-type floating gate transistors whose drain-source paths are connected in series with each other between two selection transistors.

Abstract: An error-bit generating circuit for use in a nonvolatile semiconductor memory device, particularly in an EEPROM. The circuit is capable of easily checking the deterioration of operational performance in an error checking correction device thereof, by intentionally writing bit-error data into a memory cell thereof. The error-bit generating circuit includes a parity generator for generating specified bits of parity data according to input data received from an input buffer, means for writing into a memory cell array the input data and parity data, means for, after reading out the input data and parity data from the memory cell array, correcting an error-bit among the input data and then providing the corrected data, and an error-bit generator coupled between the input buffer and the memory cell array, for generating an error-bit signal onto a selected bit of the input data in response to a control signal and an address signal.

Abstract: There is disclosed a programmable sequential code recognition circuit comprising an individual code recognition circuit for recognizing each input code, and a sequence recognition circuit for recognizing the sequency given for individual codes obtained by combination of input signals, so that a specific mode may be selected by the input combination sequentially inputted.

Abstract: A data output buffer being capable of precharging a data bus without increasing its current consumption and without having great dependency upon the process variation, whereby a READ access time of a semiconductor device is considerably reduced and the noise of source supplying voltages (Vcc, Vss) is also controlled to its least possible level in a semiconductor chip. The buffer includes means for minimizing the DC current consumption of a data bus precharge driver by feeding back an electric potential of an I/O port to an input of the precharging driver, and means for making the precharge driver operate during a specified period of time prior to providing the actual data by using an ATD pulse.

Abstract: An electrically erasable programmable semiconductor memory array for high density including a plurality of column lines; a plurality of reference lines perpendicular to the column lines; a plurality of memory strings arranged in two columns at both sides of each column line and in upper and lower rows between the reference lines, each of upper and lower memory strings at one side of each column including a first transistor and a plurality of floating gate transistors, each of upper and lower memory strings at the other side of each column including a second transistor and a plurality of floating gate transistors, drain-source paths of the first or second transistor and the floating gate transistors in each memory string being connected in series, the first and second transistors and the floating gate transistors being arranged in an array of rows and columns, gates of the first and second transistors and the floating gate transistors in the upper memory strings and the first and second transistors and the flo