Patents by Inventor Hyung-seok Hong
Hyung-seok Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190096770Abstract: Semiconductor device as provided may include a substrate with an NMOS region and a PMOS region, and a first transistor in the NMOS region that includes a first gate stack and a first source/drain region on at least one side of the first gate stack. The semiconductor device may further include a second transistor in the PMOS region that includes a second gate stack and a second source/drain region on at least one side of the second gate stack. The first gate stack may include a first insulating film, a first gate electrode layer of first thickness, additional gate electrode layers, a and a first silicon layer, which may be sequentially laminated. The second gate stack may include a second insulating film, a fourth gate electrode layer of second thickness greater than the first thickness, additional gate electrode layers, and a second silicon layer, which may be sequentially laminated.Type: ApplicationFiled: April 18, 2018Publication date: March 28, 2019Inventors: HYUNG-SEOK HONG, SUK HOON KIM, IN HEE LEE, HYE-LAN LEE
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Patent number: 9543300Abstract: Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.Type: GrantFiled: February 26, 2016Date of Patent: January 10, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Hye-Lan Lee, Hong-Bae Park, Sang-Jin Hyun, Yu-Gyun Shin, Sug-Hun Hong, Hoon-Joo Na, Hyung-Seok Hong
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Publication number: 20160204108Abstract: Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.Type: ApplicationFiled: February 26, 2016Publication date: July 14, 2016Inventors: Hye-Lan Lee, Hong-Bae Park, Sang-Jin Hyun, Yu-Gyun Shin, Sug-Hun Hong, Hoon-Joo Na, Hyung-Seok Hong
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Patent number: 9287199Abstract: Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.Type: GrantFiled: December 20, 2010Date of Patent: March 15, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hye-Lan Lee, Hong-Bae Park, Sang-Jin Hyun, Yu-Gyun Shin, Sug-Hun Hong, Hoon-Joo Na, Hyung-Seok Hong
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Patent number: 9252058Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities. In some embodiments, the MOSFETs are FinFETs, and the doping may be a conformal doping.Type: GrantFiled: June 19, 2014Date of Patent: February 2, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-Seok Hong, Sang-Jin Hyun, Hong-Bae Park, Hoon-Joo Na, Hye-Lan Lee
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Patent number: 9236313Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.Type: GrantFiled: December 8, 2014Date of Patent: January 12, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon-joo Na, Yu-gyun Shin, Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hyung-seok Hong
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Publication number: 20150093888Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.Type: ApplicationFiled: December 8, 2014Publication date: April 2, 2015Inventors: Hoon-joo Na, Yu-gyun Shin, Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hyung-seok Hong
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Publication number: 20150035077Abstract: Methods of manufacturing a MOS transistor are provided. The methods may include forming first and second trenches. The methods may further include forming first metal patterns within portions of the first and second trenches. The methods may additionally include removing the first metal patterns from the second trench while at least portions of the first metal patterns remain within the first trench. The methods may also include forming a second metal layer within the first and second trenches, the second metal layer formed on the first metal patterns within the first trench.Type: ApplicationFiled: October 21, 2014Publication date: February 5, 2015Inventors: Hye-Lan Lee, Sangjin Hyun, Yugyun Shin, Hongbae Park, Huyong Lee, Hyung-seok Hong
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Patent number: 8932922Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.Type: GrantFiled: May 26, 2011Date of Patent: January 13, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon-joo Na, Yu-gyun Shin, Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hyung-seok Hong
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Publication number: 20140302652Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities.Type: ApplicationFiled: June 19, 2014Publication date: October 9, 2014Inventors: Hyung-Seok Hong, Sang-Jin Hyun, Hong-Bae Park, Hoon-Joo Na, Hye-Lan Lee
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Publication number: 20140246726Abstract: A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.Type: ApplicationFiled: May 12, 2014Publication date: September 4, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Hoon-Joo NA, Hyung-Seok HONG, Sang-Bom KANG, Hyeok-Jun SON, June-Hee LEE, Jeong-Hee HAN, Sang-Jin HYUN
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Patent number: 8786028Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities. In some embodiments, the MOSFETs are FinFETs, and the doping may be a conformal doping.Type: GrantFiled: April 12, 2012Date of Patent: July 22, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Seok Hong, Sang-Jin Hyun, Hong-Bae Park, Hoon-Joo Na, Hye-Lan Lee
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Patent number: 8772115Abstract: A semiconductor device including a selectively nitrided gate insulating layer may be fabricated by a method that includes forming a first gate insulating layer on a substrate having a first region and a second region, performing a nitridation process on the first gate insulating layer, removing the first gate insulating layer from at least a portion of the first region to expose at least a portion of the substrate, forming a second gate insulating layer on at least the exposed portion of the first region of the substrate, thermally treating the first and second gate insulating layers in an oxygen atmosphere, forming a high-k dielectric on the first and second gate insulating layers, and forming a metal gate electrode on the high-k dielectric.Type: GrantFiled: February 19, 2013Date of Patent: July 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: HyeokJun Son, Sangjin Hyun, Sangbom Kang, SungKee Han, Sughun Hong, Hyung-seok Hong
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Patent number: 8766366Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.Type: GrantFiled: October 2, 2012Date of Patent: July 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hoonjoo Na, Sangjin Hyun, Yugyun Shin, Hongbae Park, Sughun Hong, Hye-Lan Lee, Hyung-seok Hong
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Patent number: 8748251Abstract: A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.Type: GrantFiled: June 20, 2012Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon-Joo Na, Hyung-Seok Hong, Sang-Bom Kang, Hyeok-Jun Son, June-Hee Lee, Jeong-Hee Han, Sang-Jin Hyun
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Patent number: 8633546Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor substrate with a first well region, a first gate electrode disposed on the first well region, and a first N-type capping pattern, a first P-type capping pattern, and a first gate dielectric pattern disposed between the first well region and the first gate electrode.Type: GrantFiled: July 20, 2012Date of Patent: January 21, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hongbae Park, Hagju Cho, Sunghun Hong, Sangjin Hyun, Hoonjoo Na, Hyung-seok Hong
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Publication number: 20130316525Abstract: A semiconductor device including a selectively nitrided gate insulating layer may be fabricated by a method that includes forming a first gate insulating layer on a substrate having a first region and a second region, performing a nitridation process on the first gate insulating layer, removing the first gate insulating layer from at least a portion of the first region to expose at least a portion of the substrate, forming a second gate insulating layer on at least the exposed portion of the first region of the substrate, thermally treating the first and second gate insulating layers in an oxygen atmosphere, forming a high-k dielectric on the first and second gate insulating layers, and forming a metal gate electrode on the high-k dielectric.Type: ApplicationFiled: February 19, 2013Publication date: November 28, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: HyeokJun Son, Sangjin Hyun, Sangbom Kang, SungKee Han, Sughun Hong, Hyung-seok Hong
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Patent number: 8580629Abstract: A method of fabricating a semiconductor device may include: preparing a substrate in which first and second regions are defined; forming an interlayer insulating film, which includes first and second trenches, on the substrate; forming a work function control film, which contains Al and N, along a top surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench; forming a mask pattern on the work function control film formed in the second region; injecting a work function control material into the work function control film formed in the first region to control a work function of the work function control film formed in the first region; removing the mask pattern; and forming a first metal gate electrode to fill the first trench and forming a second metal gate electrode to fill the second trench.Type: GrantFiled: September 23, 2011Date of Patent: November 12, 2013Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Hong-Bae Park, Sang-Jin Hyun, Hu-Yong Lee, Hoon-Joo Na, Jeong-Hee Han, Hye-Lan Lee, Hyung-Seok Hong
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Patent number: 8569821Abstract: Provided are a semiconductor device and a method of forming the same. The method may include forming a gate dielectric layer including a plurality of elements on a substrate; supplying a specific element to the gate dielectric layer; forming a product though reacting the specific element with at least one of the plurality of elements; and removing the product.Type: GrantFiled: September 23, 2011Date of Patent: October 29, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sangjin Hyun, Yugyun Shin, Hagju Cho, Hyung-seok Hong
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Patent number: RE49538Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.Type: GrantFiled: October 14, 2020Date of Patent: May 30, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Hoonjoo Na, Sangjin Hyun, Yugyun Shin, Hongbae Park, Sughun Hong, Hye-Lan Lee, Hyung-Seok Hong