Patents by Inventor Hyung-Shin Kwon
Hyung-Shin Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10431320Abstract: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.Type: GrantFiled: December 30, 2016Date of Patent: October 1, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-Shin Kwon, Jong-Hyoung Lim, Chang-Soo Lee, Chung-Ki Lee
-
Publication number: 20170110203Abstract: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.Type: ApplicationFiled: December 30, 2016Publication date: April 20, 2017Inventors: HYUNG-SHIN KWON, JONG-HYOUNG LIM, CHANG-SOO LEE, CHUNG-KI LEE
-
Patent number: 9053963Abstract: A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively. The first voltage being lower than the second voltage.Type: GrantFiled: July 10, 2013Date of Patent: June 9, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Chung-ki Lee, Hong-sun Hwang, Hyung-shin Kwon, Jong-hyoung Lim
-
Publication number: 20140241076Abstract: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.Type: ApplicationFiled: February 24, 2014Publication date: August 28, 2014Inventors: Hyung-Shin KWON, Jong-Hyoung Lim, Chang-Soo Lee, Chung-Ki Lee
-
Publication number: 20140092680Abstract: A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively. The first voltage being lower than the second voltage.Type: ApplicationFiled: July 10, 2013Publication date: April 3, 2014Inventors: Chung-ki LEE, Hong-sun HWANG, Hyung-shin KWON, Jong-hyoung LIM
-
Patent number: 8619484Abstract: A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals.Type: GrantFiled: September 8, 2011Date of Patent: December 31, 2013Assignee: Samsung Electronics Co., LtdInventors: Jong Hyoung Lim, Sang Seok Kang, Hyung Shin Kwon
-
Patent number: 8558347Abstract: A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.Type: GrantFiled: February 28, 2013Date of Patent: October 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Shin Kwon, Hyung-Dong Kim
-
Publication number: 20130175667Abstract: A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.Type: ApplicationFiled: February 28, 2013Publication date: July 11, 2013Inventors: Hyung-Shin Kwon, Hyung-Dong Kim
-
Patent number: 8415225Abstract: A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.Type: GrantFiled: August 30, 2011Date of Patent: April 9, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Shin Kwon, Hyung-Dong Kim
-
Publication number: 20120063251Abstract: A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals.Type: ApplicationFiled: September 8, 2011Publication date: March 15, 2012Inventors: Jong Hyoung LIM, Sang Seok Kang, Hyung Shin Kwon
-
Publication number: 20120052648Abstract: A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.Type: ApplicationFiled: August 30, 2011Publication date: March 1, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-Shin Kwon, Hyung-Dong Kim
-
Patent number: 7696048Abstract: A semiconductor device is formed with a normal, non-recessed, spacer structure in a cell region and a recessed spacer structure in a peripheral region. The recessed spacer structure is formed as by etch masking those in the cell region and exposing those in the peripheral region, then performing an etch process. The increased height of the cell region spacers is adapted to further prevent over-etching during gate interconnect formation which would otherwise result in etching through the spacer to the substrate and subsequent short circuit. Therefore, it is also possible to prevent bridge defects due to over-etching, which occurs because the barrier metal layer for a subsequent interconnection contact is accidentally connected to the underlying substrate. Also, since the recessed spacer structure is provided in the peripheral region, it is possible to remarkably enhance a resistance distribution of a cobalt silicide layer occurring in a gate line width of 100 nm or less.Type: GrantFiled: June 19, 2006Date of Patent: April 13, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Shin Kwon, Seug-Gyu Kim
-
Patent number: 7385260Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 ? in the impurity region.Type: GrantFiled: April 21, 2004Date of Patent: June 10, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Shin Kwon, Joon-Yong Joo, Kwang-Ok Koh, Sung-Bong Kim
-
Patent number: 7348231Abstract: Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substrate. A first insulating layer is provided on the NMOS transistor. The first insulating layer has a first compressive stress. A second insulating layer is provided on the PMOS transistor. The second insulating layer has a second compressive stress and a stress relief ratio higher than a stress relief ratio of the first insulating layer. A thermal treatment process is performed on the first insulating layer and the second insulating layer such that the second compressive stress of the second insulating layer is lower than the first compressive stress of the first insulating layer. Related devices are also provided.Type: GrantFiled: December 30, 2005Date of Patent: March 25, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Shin Kwon, Dong-Won Lee, Jun-Beom Park
-
Patent number: 7312144Abstract: An interconnection structure is provided by forming a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode.Type: GrantFiled: September 2, 2004Date of Patent: December 25, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Seok Cho, Soon-Moon Jung, Sung-Bong Kim, Hyung-Shin Kwon
-
Publication number: 20070293030Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 ? in the impurity region.Type: ApplicationFiled: August 27, 2007Publication date: December 20, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-Shin KWON, Joon-Yong JOO, Kwang-Ok KOH, Sung-Bong KIM
-
Publication number: 20070290280Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 ? in the impurity region.Type: ApplicationFiled: August 27, 2007Publication date: December 20, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-Shin KWON, Joon-Yong JOO, Kwang-Ok KOH, Sung-Bong KIM
-
Publication number: 20070037336Abstract: A semiconductor device is formed with a normal, non-recessed, spacer structure in a cell region and a recessed spacer structure in a peripheral region. The recessed spacer structure is formed as by etch masking those in the cell region and exposing those in the peripheral region, then performing an etch process. The increased height of the cell region spacers is adapted to further prevent over-etching during gate interconnect formation which would otherwise result in etching through the spacer to the substrate and subsequent short circuit. Therefore, it is also possible to prevent bridge defects due to over-etching, which occurs because the barrier metal layer for a subsequent interconnection contact is accidentally connected to the underlying substrate. Also, since the recessed spacer structure is provided in the peripheral region, it is possible to remarkably enhance a resistance distribution of a cobalt silicide layer occurring in a gate line width of 100 nm or less.Type: ApplicationFiled: June 19, 2006Publication date: February 15, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-Shin KWON, Seug-Gyu KIM
-
Patent number: 7172944Abstract: The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating layer pattern is protruded from the edge of the second insulating layer pattern to be covered with the silicon epitaxial layer whose predetermined region is silicided.Type: GrantFiled: November 18, 2005Date of Patent: February 6, 2007Assignee: Samsung Electronics Co., Ltd.Inventor: Hyung-Shin Kwon
-
Patent number: 7151031Abstract: Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second active area of the semiconductor substrate. The second gate pattern has a top width that is wider than a bottom width of the second gate pattern. Semiconductor device are fabricated by forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate. A mask insulation layer is formed on the semiconductor substrate that includes the first gate pattern. First and second gate openings respectively exposing second and third active regions of the semiconductor substrate are formed by patterning the mask insulation layer. Second and third gate insulation layers respectively are formed on second and third active regions exposed in the first and second gate openings.Type: GrantFiled: March 5, 2004Date of Patent: December 19, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Shin Kwon, Soon-Moon Jung