Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.

Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.

Abstract: Semiconductor devices are provided. The semiconductor devices include a first fin; a first gate electrode intersecting the first fin; a first elevated source and/or drain on respective sides of the first gate electrode on the first fin; and a first field dielectric film adjacent the first fin. The first field dielectric film includes a first part below a top surface of the first fin and a second part protruding from the first part and above a top surface of the first fin that makes contact with the first elevated source and/or drain.

Abstract: A metal wiring forming method in a semiconductor device can include forming an interlayer insulating film on a lower metal wiring, the first interlayer insulating film having a non-planar upper surface; forming a stop layer on the interlayer insulating film and over the lower metal wiring; forming an interlayer insulating film pattern on the stop layer, wherein an upper surface of the interlayer insulating film pattern and an upper surface of the stop layer are substantially coplanar; removing a portion of the stop layer to form a stop layer pattern, wherein a portion of the interlayer insulating film over the lower metal wiring is exposed by the stop layer pattern; and etching the exposed portion of the interlayer insulating film to form a via hole therethrough, wherein the lower metal wiring is exposed by the via hole.

Abstract: A metal wiring forming method in a semiconductor device can include forming an interlayer insulating film on a lower metal wiring, the first interlayer insulating film having a non-planar upper surface; forming a stop layer on the interlayer insulating film and over the lower metal wiring; forming an interlayer insulating film pattern on the stop layer, wherein an upper surface of the interlayer insulating film pattern and an upper surface of the stop layer are substantially coplanar; removing a portion of the stop layer to form a stop layer pattern, wherein a portion of the interlayer insulating film over the lower metal wiring is exposed by the stop layer pattern; and etching the exposed portion of the interlayer insulating film to form a via hole therethrough, wherein the lower metal wiring is exposed by the via hole.