Patents by Inventor Hyung-suk Jung

Hyung-suk Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929389
    Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: March 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn-soo Kim, Seung-min Ryu, Chang-su Woo, Hyung-suk Jung, Kyu-ho Cho, Youn-joung Cho
  • Publication number: 20230361161
    Abstract: There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film.
    Type: Application
    Filed: July 6, 2023
    Publication date: November 9, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Han Jin LIM, Ki Nam KIM, Hyung Suk JUNG, Kyoo Ho JUNG, Ki Hyun HWANG
  • Publication number: 20230260783
    Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji-woon PARK, Jin-su LEE, Hyung-suk JUNG
  • Patent number: 11728372
    Abstract: There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: August 15, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han Jin Lim, Ki Nam Kim, Hyung Suk Jung, Kyoo Ho Jung, Ki Hyun Hwang
  • Patent number: 11682555
    Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: June 20, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-woon Park, Jin-su Lee, Hyung-suk Jung
  • Publication number: 20230061185
    Abstract: A semiconductor device is provided. The semiconductor device comprises a lower electrode, a lower dielectric layer on the lower electrode, an upper electrode on the lower dielectric layer, an upper dielectric layer formed between the lower dielectric layer and the upper electrode, and an interposed electrode film formed between the lower dielectric layer and the upper dielectric layer, wherein the upper dielectric layer includes titanium oxide.
    Type: Application
    Filed: March 30, 2022
    Publication date: March 2, 2023
    Inventors: Intak JEON, Han Jin LIM, Hyung Suk JUNG, Jae Hyoung CHOI
  • Patent number: 11588012
    Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: February 21, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-goo Kang, Sang-yeol Kang, Youn-soo Kim, Jin-su Lee, Hyung-suk Jung, Kyu-ho Cho
  • Publication number: 20220231117
    Abstract: There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film.
    Type: Application
    Filed: April 6, 2022
    Publication date: July 21, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Han Jin LIM, Ki Nam KIM, Hyung Suk JUNG, Kyoo Ho JUNG, Ki Hyun HWANG
  • Patent number: 11322578
    Abstract: There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 3, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han Jin Lim, Ki Nam Kim, Hyung Suk Jung, Kyoo Ho Jung, Ki Hyun Hwang
  • Publication number: 20210273039
    Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.
    Type: Application
    Filed: May 19, 2021
    Publication date: September 2, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Youn-soo KIM, Seung-min RYU, Chang-su WOO, Hyung-suk JUNG, Kyu-ho CHO, Youn-joung CHO
  • Publication number: 20210225636
    Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.
    Type: Application
    Filed: April 7, 2021
    Publication date: July 22, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji-woon PARK, Jin-su LEE, Hyung-suk JUNG
  • Publication number: 20210202693
    Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.
    Type: Application
    Filed: March 12, 2021
    Publication date: July 1, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun-goo KANG, Sang-yeol KANG, Youn-soo KIM, Jin-su LEE, Hyung-suk JUNG, Kyu-ho CHO
  • Patent number: 11043553
    Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: June 22, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn-soo Kim, Seung-min Ryu, Chang-su Woo, Hyung-suk Jung, Kyu-ho Cho, Youn-joung Cho
  • Patent number: 10991574
    Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: April 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-woon Park, Jin-su Lee, Hyung-suk Jung
  • Patent number: 10978552
    Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-goo Kang, Sang-yeol Kang, Youn-soo Kim, Jin-su Lee, Hyung-suk Jung, Kyu-ho Cho
  • Publication number: 20200286985
    Abstract: There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film.
    Type: Application
    Filed: October 2, 2019
    Publication date: September 10, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Han Jin Lim, Ki Nam Kim, Hyung Suk Jung, Kyoo Ho Jung, Ki Hyun Hwang
  • Publication number: 20200111660
    Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.
    Type: Application
    Filed: May 9, 2019
    Publication date: April 9, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji-woon Park, Jin-su Lee, Hyung-suk Jung
  • Publication number: 20200091275
    Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.
    Type: Application
    Filed: July 24, 2019
    Publication date: March 19, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Youn-soo Kim, Seung-min Ryu, Chang-su Woo, Hyung-suk Jung, Kyu-ho Cho, Youn-joung Cho
  • Patent number: 10566433
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor formed in the first region and formed by a first gate line including a first lower metal-containing layer and a first upper metal-containing layer, and a second transistor formed in the second region and formed by a second gate line having an equal width to that of the first gate line and including a second lower metal-containing layer and a second upper metal-containing layer on the second upper metal-containing layer, wherein each of an uppermost end of the first upper metal-containing layer and an uppermost end of the second lower metal-containing layer has a higher level than an uppermost end of the first lower metal-containing layer.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Hyuk Yim, Wan-Don Kim, Jong-Han Lee, Hyung-Suk Jung, Sang-Jin Hyun
  • Patent number: 10559687
    Abstract: A semiconductor device including a substrate; a first and second active region on the substrate; a first recess intersecting with the first active region; a second recess intersecting with the second active region; a gate spacer extending along sidewalls of the first and second recess; a first lower high-k dielectric film in the first recess and including a first high-k dielectric material in a first concentration and a second high-k dielectric material; a second lower high-k dielectric film in the second recess and including the first high-k dielectric material in a second concentration that is greater than the first concentration, and the second high-k dielectric material; a first metal-containing film on the first lower high-k dielectric film and including silicon in a third concentration; and a second metal-containing film on the second lower high-k dielectric film and including silicon in a fourth concentration that is smaller than the third concentration.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Yeol Song, Su Young Bae, Dong Soo Lee, Hyung Suk Jung, Sang Jin Hyun