Abstract: A semiconductor package includes: a substrate; a semiconductor chip provided on the substrate; a plurality of heat dissipation reinforcements provided on the substrate; and an encapsulant, on the substrate, molding the semiconductor chip and the plurality of heat dissipation reinforcements. Each of the plurality of heat dissipation reinforcements has an elongated shape, and extends along lateral surfaces and an upper surface of the semiconductor chip at a predetermined interval from the semiconductor chip.

Abstract: A semiconductor package includes a lower chip. A chip stacked structure is arranged on the lower chip. The chip stacked structure includes a plurality of upper chips. An underfill layer is disposed between the lower chip and the chip stacked structure and between the plurality of upper chips. A molding layer surrounds the underfill layer and the chip stacked structure. The lower chip has at least one lower trench positioned on an upper surface of the lower chip. At least one of the plurality of upper chips has at least one upper trench on an upper surface of the at least one of the plurality of upper chips.

Abstract: A semiconductor package includes; a package substrate including an upper surface with a bonding pad, a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region including a connection pad and an open edge region including a dam structure including dummy bumps, a bonding wire having a first height above the upper surface of the lower semiconductor chip and connecting the bonding pad and the connection pad, an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip using an inter-chip bonding layer, and a molding portion on the package substrate and substantially surrounding the lower semiconductor chip and the upper semiconductor chip.

Abstract: A semiconductor package device includes a package substrate, an interposer on the package substrate, a semiconductor package on the interposer, and an under-fill between the interposer and the semiconductor package. The interposer includes at least one first trench at an upper portion of the interposer that extends in a first direction parallel to a top surface of the package substrate. The at least one first trench vertically overlaps an edge region of the semiconductor package. The under-fill fills at least a portion of the at least one trench.

Abstract: Disclosed is a semiconductor module comprising a module substrate having a top surface and a bottom surface that are opposite to each other, a plurality of semiconductor packages on the top surface of the module substrate and arranged in a first direction parallel to the top surface of the module substrate, and a clip structure on the top surface of the module substrate and spaced apart from the plurality of semiconductor packages in the first direction. The clip structure includes a body part on the top surface of the module substrate and spaced apart from the plurality of semiconductor packages in the first direction, and a connection part that extends from the body part across a lateral surface of the module substrate onto the bottom surface of the module substrate.

Abstract: A semiconductor package includes; a package substrate including an upper surface with a bonding pad, a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region including a connection pad and an open edge region including a dam structure including dummy bumps, a bonding wire having a first height above the upper surface of the lower semiconductor chip and connecting the bonding pad and the connection pad, an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip using an inter-chip bonding layer, and a molding portion on the package substrate and substantially surrounding the lower semiconductor chip and the upper semiconductor chip.

Abstract: A semiconductor package device includes a package substrate, an interposer on the package substrate, a semiconductor package on the interposer, and an under-fill between the interposer and the semiconductor package. The interposer includes at least one first trench at an upper portion of the interposer that extends in a first direction parallel to a top surface of the package substrate. The at least one first trench vertically overlaps an edge region of the semiconductor package. The under-fill fills at least a portion of the at least one trench.