Patents by Inventor Hyun-Jun Sim
Hyun-Jun Sim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240144270Abstract: A vehicle-to-everything (V2X) communication-based electronic toll collection system (ETCS) according to an embodiment of the present invention includes at least one roadside unit (RSU), a token issuer checking a de-identified token of a vehicle by communicating with an on-board unit (OBU) of the vehicle via the at least one roadside unit, and a clearing house communicating with the token issuer and charging a toll to a driver/owner of the vehicle. The token issuer generates toll information of the vehicle based on the de-identified token of the vehicle and location information of the at least one roadside unit involved in checking the de-identified token.Type: ApplicationFiled: November 28, 2022Publication date: May 2, 2024Inventors: Duk Soo KIM, Eui Seok KIM, Sang Gyoo SIM, Ki Ho JOO, Jung Won LEE, Jong Guk LEE, Jung Wook KIM, Sang Seok LEE, Sang Min LEE, Sook Jun GWEON, Hyun Kyung PARK
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Patent number: 10797160Abstract: A method of fabricating a semiconductor device may include forming a fin structure on a substrate; forming an interface film having a first thickness on the fin structure using a first process; forming a gate dielectric film having a second thickness on the interface film using a second process different from the first process; and densifying the gate dielectric film using a third process different from the first and second processes. The second thickness may be greater than the first thickness, and the first thickness of the interface film may be unchanged after the densifying of the gate dielectric film.Type: GrantFiled: October 2, 2018Date of Patent: October 6, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Jun Sim, Won-Oh Seo, Sun-Jung Kim, Ki-Yeon Park
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Patent number: 10411011Abstract: A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.Type: GrantFiled: July 5, 2018Date of Patent: September 10, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Kook-Tae Kim, Ho-Sung Son, Dong-Suk Shin, Hyun-Jun Sim, Ju-Ri Lee, Sung-Uk Jang
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Publication number: 20190237563Abstract: A method of fabricating a semiconductor device may include forming a fin structure on a substrate; forming an interface film having a first thickness on the fin structure using a first process; forming a gate dielectric film having a second thickness on the interface film using a second process different from the first process; and densifying the gate dielectric film using a third process different from the first and second processes. The second thickness may be greater than the first thickness, and the first thickness of the interface film may be unchanged after the densifying of the gate dielectric film.Type: ApplicationFiled: October 2, 2018Publication date: August 1, 2019Inventors: HYUN-JUN SIM, WON-OH SEO, SUN-JUNG KIM, KI-YEON PARK
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Publication number: 20180331105Abstract: A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.Type: ApplicationFiled: July 5, 2018Publication date: November 15, 2018Inventors: KOOK-TAE KIM, HO-SUNG SON, DONG-SUK SHIN, HYUN-JUN SIM, JU-RI LEE, SUNG-UK JANG
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Patent number: 10043806Abstract: A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.Type: GrantFiled: September 26, 2016Date of Patent: August 7, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Kook-Tae Kim, Ho-Sung Son, Dong-Suk Shin, Hyun-Jun Sim, Ju-Ri Lee, Sung-Uk Jang
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Publication number: 20170133379Abstract: A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.Type: ApplicationFiled: September 26, 2016Publication date: May 11, 2017Inventors: KOOK-TAE KIM, HO-SUNG SON, DONG-SUK SHIN, HYUN-JUN SIM, JU-RI LEE, SUNG-UK JANG
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Patent number: 9397196Abstract: In a method of manufacturing a semiconductor device, a preliminary gate insulation layer is formed on a substrate, and at least a portion of the substrate serves as a channel region. A hydrogen plasma treatment is performed on the preliminary gate insulation layer to form a gate insulation layer, and the hydrogen plasma treatment supplying a hydrogen-containing gas and an inert gas supply in a chamber via different gas supply parts to form a hydrogen plasma region and an inert gas plasma region in the chamber, respectively. A gate electrode is formed on the gate insulation layer, and impurity regions are formed at upper portions of the substrate adjacent to the gate electrode.Type: GrantFiled: April 29, 2015Date of Patent: July 19, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Jun Sim, Jae-Young Park, Sun-Young Lee
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Publication number: 20160079395Abstract: In a method of manufacturing a semiconductor device, a preliminary gate insulation layer is formed on a substrate, and at least a portion of the substrate serves as a channel region. A hydrogen plasma treatment is performed on the preliminary gate insulation layer to form a gate insulation layer, and the hydrogen plasma treatment supplying a hydrogen-containing gas and an inert gas supply in a chamber via different gas supply parts to form a hydrogen plasma region and an inert gas plasma region in the chamber, respectively. A gate electrode is formed on the gate insulation layer, and impurity regions are formed at upper portions of the substrate adjacent to the gate electrode.Type: ApplicationFiled: April 29, 2015Publication date: March 17, 2016Inventors: Hyun-Jun SIM, Jae-Young PARK, Sun-Young LEE
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Patent number: 8759182Abstract: A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.Type: GrantFiled: April 30, 2012Date of Patent: June 24, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Jun Sim, Jae-Young Park, Hyun-Seung Kim, Sang-Bom Kang, Sun-Ghil Lee, Hyun-Deok Yang, Kang-Hun Moon, Han-Ki Lee, Sang-Mi Choi
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Patent number: 8698281Abstract: A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.Type: GrantFiled: October 19, 2012Date of Patent: April 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: In-Gyu Baek, Hyun-Jun Sim, Jin-Shi Zhao, Eun-Kyung Yim
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Patent number: 8451645Abstract: A variable resistance memory device includes a variable resistance memory cell, and a by-pass circuit configured to electrically by-pass a programming pulse supplied to the variable resistance memory cell after a resistive state of the variable resistance memory cell has changed in response to the programming pulse.Type: GrantFiled: August 6, 2010Date of Patent: May 28, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Sik Yoon, Min-Young Park, In-Gyu Baek, Hyun-Jun Sim, Jin-Shi Zhao
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Patent number: 8358527Abstract: Multi-level nonvolatile memory devices using variable resistive elements, the multi-level nonvolatile memory devices including a word line, a bit line, and a multi-level memory cell coupled between the word line and the bit line, the multi-level memory cell having first resistance level and a second resistance level higher than the first resistance level when the first and second write biases having the same polarity are applied thereto, and a third resistance level and a fourth resistance level ranging between the first and second resistance levels, when third and fourth write biases having different polarities from each other are applied thereto.Type: GrantFiled: February 16, 2010Date of Patent: January 22, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: In-Gyu Baek, Hyun-Jun Sim, Hong-Sik Yoon, Jin-Shi Zhao, Min-Young Park
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Publication number: 20120306004Abstract: Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.Type: ApplicationFiled: August 14, 2012Publication date: December 6, 2012Inventors: Hong Sik Yoon, Jinshi Zhao, Ingyu Baek, Hyun Jun Sim, Minyoung Park
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Publication number: 20120299154Abstract: A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.Type: ApplicationFiled: April 30, 2012Publication date: November 29, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Jun Sim, Jae-Young Park, Hyun-Seung Kim, Sang-Bom Kang, Sun-Ghil Lee, Hyun-Deok Yang, Kang-Hun Moon, Han-Ki Lee, Sang-Mi Choi
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Patent number: 8314003Abstract: A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.Type: GrantFiled: May 5, 2011Date of Patent: November 20, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: In-Gyu Baek, Hyun-Jun Sim, Jin-Shi Zhao, Eun-Kyung Yim
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Patent number: 8264018Abstract: Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.Type: GrantFiled: May 11, 2010Date of Patent: September 11, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hong Sik Yoon, Jinshi Zhao, Ingyu Baek, Hyun Jun Sim, Minyoung Park
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Publication number: 20120142159Abstract: Methods for fabricating a semiconductor device are provided wherein, in an embodiment, the method includes the steps of forming a gate electrode on a semiconductor substrate, forming a trench by recessing the semiconductor substrate in the vicinity of the gate electrode, doping an anti-diffusion ion into a portion of the semiconductor substrate in the trench, and growing an impurity-doped epitaxial layer on the semiconductor substrate doped with the anti-diffusion ion.Type: ApplicationFiled: September 23, 2011Publication date: June 7, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Gon Kim, Sang-Bom Kang, Jae-Young Park, Kang-Hun Moon, Hyun-Jun Sim, Seung-Hun Lee, Han-Ki Lee, Hyun-Seung Kim
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Patent number: 8058097Abstract: Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.Type: GrantFiled: May 20, 2010Date of Patent: November 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-Eun Lee, Dae-Kyom Kim, Jun-Ho Jeong, Se-Chung Oh, Kyung-Tae Nam, Hyun-Jun Sim
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Publication number: 20110204315Abstract: A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.Type: ApplicationFiled: May 5, 2011Publication date: August 25, 2011Inventors: In-Gyu Baek, Hyun-Jun Sim, Jin-Shi Zhao, Eun-Kyung Yim