Abstract: A vacuum suction head may include a holder including a through hole formed therein, a suction pad surrounding at least a portion of a side surface of the holder, and a packing pad on a lower surface of the holder. The suction pad may protrude below a lower surface of the holder. The packing pad may include a cutout part. The cutout part may allow a space between the suction pad and the packing pad such that the space and the through hole may be in fluid communication with each other.

Abstract: A display apparatus including a display and a supporter. The supporter being mounted on the display and configured to support the display and rotate the display module between a first position and a second position. The supporter including a drive motor, a first gear, and a detection sensor. The drive motor configured to supply a driving force to rotate the display. The first gear configured to rotate together with the display by receiving the driving force from the drive motor. The detection sensor configured to detect a rotation amount of a second gear configured to rotate in with the first gear.

Abstract: A driving circuit includes: a display driver to generate a horizontal synchronization signal and a vertical synchronization signal according to a first clock signal of a first oscillator; a sensor driver to generate a touch signal according to a second clock signal of a second oscillator; and a determination circuit to detect a cycle of at least one of the horizontal synchronization signal or the vertical synchronization signal according to the second clock signal, and output a detection signal when the cycle is out of a range. The determination circuit is a part of the display driver or the sensor driver.

Abstract: The present invention relates to a method for determining the DNA quality of a biological sample and, more specifically, to a method for determining the DNA quality of a biological sample by performing a quantitative polymerase chain reaction (PCR) using primers capable of amplifying a target gene, a method for preparing the primers used in the method, and a method for standardizing the amount of detected target gene mutation by using the determined DNA quality. The method of the present invention enables objective evaluation of the DNA quality of a biological sample used in gene analysis and the presentation of objective results on the expression ratio of a gene mutation, thereby providing reliable information in the fields of clinical research and companion diagnosis.

Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.

Abstract: Provided is a conjugate for photodynamic diagnosis or treatment in which a peptide binds with a photosensitizer via an intracellularly degradable linkage, and a composition for photodynamic diagnosis or treatment including the same. The conjugate generates no fluorescent signal and reactive oxygen in normal tissues or during the circulation in the blood by quenching a fluorescent signal and reactive oxygen generation ability of the photosensitizer. After the conjugate is selectively absorbed into target cells, a linker is degraded in cells to increase the distance between tryptophan included in the peptide and the photosensitizer, and the quenching action is terminated to generate a strong fluorescence signal and induce active generation of reactive oxygen. The conjugate has high tissue permeability, shows a high photodynamic therapeutic effect in only target cells while being safe in normal cells, and can obtain a good diagnostic image having a high ratio of target signal to background.

Abstract: The present disclosure relates to a polyethylene resin composition capable of improving transparency and moisture barrier properties without deterioration in physical properties of a film, and a film including the same, wherein the polyethylene resin composition comprises a nucleating agent and a lubricant both containing a cation of a same metal selected from Group 2 or Group 12 metals.

Abstract: The present invention provides a pharmaceutical composition for prevention or treatment of a stress disease and depression, the pharmaceutical composition be safely useable without toxicity and side effects by using an extract of leaves of Vaccinium bracteatum Thunb., which is natural resource of Korea, so that the reduction of manufacturing and production costs and the import substitution and export effects can be expected through the replacement of a raw material for preparation with a plant inhabiting in nature.

Abstract: A display apparatus including a display and a supporter. The supporter being mounted on the display and configured to support the display and rotate the display module between a first position and a second position. The supporter including a drive motor, a first gear, and a detection sensor. The drive motor configured to supply a driving force to rotate the display. The first gear configured to rotate together with the display by receiving the driving force from the drive motor. The detection sensor configured to detect a rotation amount of a second gear configured to rotate in with the first gear.

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

Abstract: A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.

Abstract: A security circuit includes an electrical fuse read only memory (ROM) including a plurality of electrical fuse units. The electrical fuse units are arranged to correspond to bit values of an initial security key before the electrical fuse ROM is programmed.

Abstract: A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.

Abstract: A security circuit includes an electrical fuse read only memory (ROM) including a plurality of electrical fuse units. The electrical fuse units are arranged to correspond to bit values of an initial security key before the electrical fuse ROM is programmed.

Abstract: A security circuit includes an electrical fuse read only memory (ROM) including a plurality of electrical fuse units. The electrical fuse units are arranged to correspond to bit values of an initial security key before the electrical fuse ROM is programmed.

Abstract: A driver may include a driving unit and/or a boosting unit. The driving unit may be configured to provide a driving signal to at least one load. The boosting unit may be configured to boost the driving signal based on transition time points of the driving signal to reduce a distortion of the driving signal. The transition time points may be time points during a transition of the driving signal from a first level to a second level.

Abstract: A security circuit includes an electrical fuse read only memory (ROM) including a plurality of electrical fuse units. The electrical fuse units are arranged to correspond to bit values of an initial security key before the electrical fuse ROM is programmed.